Memory cell having an integrated two-terminal current limiting resistor
View Patent ↗A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
1. A memory cell comprising:
a first electrode layer;
a variable resistance layer comprising a resistive switching material capable of switching between two resistive states upon application of a predetermined voltage to the variable resistance layer; and
a resistor structure,
the resistor structure comprising a lightly doped polysilicon layer,
wherein the first electrode layer, the resistance layer, and the resistor structure form a stack and are interconnected in series within the stack,
wherein the lightly doped polysilicon layer has a dopant concentration of less than 10 16 atoms/cm 3 , and
wherein the lightly doped polysilicon layer has a resistivity of at least 1 Ohm-cm in a direction along the height of the stack.
2. The memory cell of claim 1 , wherein the resistor structure is operable a second electrode layer of the memory cell.
3. The memory cell of claim 2 , wherein the lightly doped polysilicon layer has a resistivity of less than 0.001 Ohm-cm within a plane normal to the height of the stack.
4. The memory cell of claim 2 , wherein the resistor structure is shared by multiple memory cells.
5. The memory cell of claim 1 , wherein the resistor structure is homogeneous and directly interfaces the variable resistance layer.
6. The memory cell of claim 1 , wherein the resistor structure comprises multiple layers having different compositions, and wherein the multiple layers comprise a non-linear resistive layer comprising the lightly doped polysilicon layer.
7. The memory cell of claim 6 , wherein the multiple layers further comprise an intermediate electrode layer, the intermediate electrode layer interfaces with the variable resistance layer and disposed between the non-linear resistive layer and the variable resistance layer.
8. The memory cell of claim 7 , wherein the intermediate electrode layer comprises a highly doped polysilicon having a dopant concentration of at least 1018 atoms/cm3.
9. The memory cell of claim 6 , wherein the multiple layers further comprise a diffusion barrier layer, the diffusion barrier layer disposed between the current limiting layer and the variable resistance layer.
10. The memory cell of claim 9 , wherein the diffusion barrier layer comprises one of titanium nitride, tantalum nitride, indium oxide, copper silicide, or tungsten nitride.
11. The memory cell of claim 1 , wherein the resistive switching material comprises one of hafnium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, yttrium oxides, dysprosium oxide, ytterbium oxide, or zirconium oxide.
12. The memory cell of claim 1 , wherein the electrode layer comprises one of highly doped polysilicon, titanium nitride, aluminum, or tungsten.
13. The memory cell of claim 1 , wherein the lightly doped polysilicon layer comprises one of phosphorus, arsenic, or antimony.
14. The memory cell of claim 1 , wherein the lightly doped polysilicon layer comprises one of boron, aluminum, indium, or gallium.
15. The memory cell of claim 1 , wherein the lightly doped polysilicon layer has a breakdown voltage of at least 8V.
16. The memory cell of claim 1 , wherein the resistor structure has a thickness of less than 200 Angstroms.
17. The memory cell of claim 1 , wherein the resistor structure has a thickness of less than 50 Angstroms.
18. The memory cell of claim 1 , wherein the lightly doped polysilicon layer has a resistivity of less than 0.001 Ohm-cm within a plane normal to the height of the stack.
19. The memory cell of claim 1 , wherein the lightly doped polysilicon layer has a resistivity of less than 10-6 Ohm-cm within a plane normal to the height of the stack.
20. A memory cell comprising:
a first electrode layer comprising titanium nitride;
a variable resistance layer comprising a resistive switching material capable of switching between two resistive states upon application of a predetermined voltage to the variable resistance layer the resistive switching materials comprising transitional metal oxide; and
a resistor structure,
the resistor structure comprising a lightly doped polysilicon layer, a highly doped polysilicon layer, and a diffusion barrier layer disposed between the lightly doped polysilicon layer and the highly doped polysilicon layer,
wherein the first electrode layer, the resistance layer, and the resistor structure form a stack and are interconnected in series within the stack,
wherein the lightly doped polysilicon layer having a dopant concentration of less than 10 16 atoms/cm 3 ,
wherein the lightly doped polysilicon layer has a resistivity of at least 1 Ohm-cm in a direction along the height of the stack,
wherein the highly doped polysilicon directly interfaces the variable resistance layer and has a dopant concentration of less than 10 18 atoms/cm 3 .