Active area shaping of III-nitride devices utilizing multiple dielectric materials
In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate.
1. A III-nitride semiconductor device comprising:
a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas;
a dielectric body situated over said III-nitride heterojunction and comprising a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than said first dielectric material;
first and second ohmic electrodes extending through said dielectric body to contact said III-nitride heterojunction;
a gate dielectric situated between said III-nitride heterojunction and said dielectric body including said first dielectric layer and said second dielectric layer, said gate dielectric extending from said first ohmic electrode to said second ohmic electrode;
a gate well being of a first width defined by said first dielectric layer, and being of a second width defined by said second dielectric layer, said second width being greater than said first width;
a gate arrangement situated in said gate well and comprising a gate electrode integrated with a field plate.
2. The III-nitride semiconductor device of claim 1 , wherein said first dielectric material is an oxide and said second dielectric material is a nitride.
3. The III-nitride semiconductor device of claim 1 , wherein said first dielectric material is a nitride and said second dielectric material is an oxide.
4. The III-nitride semiconductor device of claim 1 , wherein said first width is defined by an opening in said first dielectric layer.
5. The III-nitride semiconductor device of claim 1 , wherein said second width is defined by an opening in said second dielectric layer.
6. The III-nitride semiconductor device of claim 1 , wherein said field plate is situated over said first dielectric layer.
7. The III-nitride semiconductor device of claim 1 , wherein said field plate is situated over said second dielectric layer.
8. The III-nitride semiconductor device of claim 1 , wherein first and second ledges of said first dielectric layer define said first width of said gate well.
9. The Ill-nitride semiconductor device of claim 1 , wherein said dielectric body is configured to passivate said first III-nitride body.
10. The III-nitride semiconductor device of claim 1 , wherein said field plate is a drain-side field plate.
11. The III-nitride semiconductor device of claim 1 , wherein said field plate is a source-side field plate.
12. A III-nitride semiconductor device, comprising:
a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas;
a dielectric body situated over said III-nitride heterojunction and comprising a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than said first dielectric material;
first and second ohmic electrodes extending through said dielectric body to contact said III-nitride heterojunction;
a gate dielectric situated between said III-nitride heterojunction and said dielectric body including said first dielectric layer and said second dielectric layer, said gate dielectric extending from said first ohmic electrode to said second ohmic electrode;
a gate arrangement having a gate electrode situated in an opening in said first dielectric layer, and a field plate situated in an opening in said second dielectric layer.
13. The III-nitride semiconductor device of claim 12 , wherein said first dielectric material is an oxide and said second dielectric material is a nitride.
14. The III-nitride semiconductor device of claim 12 , wherein said first dielectric material is a nitride and said second dielectric material is an oxide.
15. The III-nitride semiconductor device of claim 12 , wherein said opening in said second dielectric layer is wider than said opening in said first dielectric layer.
16. The III-nitride semiconductor device of claim 12 , wherein said gate arrangement fills said opening in said first dielectric layer and said opening in said second dielectric layer.
17. The III-nitride semiconductor device of claim 12 , wherein said field plate is situated over said first dielectric layer.
18. The III-nitride semiconductor device of claim 12 , wherein said field plate is situated over said second dielectric layer.
19. The III-nitride semiconductor device of claim 12 , wherein first and second ledges of said first dielectric layer define said opening in said first dielectric layer.
20. The III-nitride semiconductor device of claim 12 , wherein said field plate is a drain-side field plate.