Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes
View Patent ↗A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.
1. A memory interface circuit for read operations, comprising:
one or more controller circuits for controlling the memory interface circuit;
one or more read data delay circuits for providing CAS latency compensation for a plurality of byte lanes, by programmably delaying the read data for each byte lane in response to control settings;
wherein the control settings for the one or more read data delay circuits for providing CAS latency compensation are determined and set using said one or more controller circuits according to a dynamic calibration procedure performed from time to time during functional operation of the memory interface circuit; and
wherein determining and setting the control settings for the one or more read data delay circuits for providing CAS latency compensation for the plurality of byte lanes is performed independently for each byte lane and parallelly among the plurality of byte lanes.
2. The memory interface circuit of claim 1 , wherein the one or more read data delay circuits for providing CAS latency compensation comprise at least two or more clocked storage elements.
3. The memory interface circuit of claim 2 , wherein a plurality of clocked storage elements among the at least two or more clocked storage elements are in series.
4. The memory interface circuit of claim 3 , wherein the one or more read data delay circuits for providing CAS latency compensation, delay read data by variable numbers of clock edges according to the control settings.
5. The memory interface circuit of claim 1 , wherein the dynamic calibration procedure is performed from time to time during functional operation of a system circuit including the memory interface circuit and at least one memory device connected to the memory interface circuit.
6. The memory interface circuit of claim 1 , further comprising one or more expected read data memories for storing data values corresponding to expected values for read data at one or more specific CAS latency compensation delay settings.
7. The memory interface circuit of claim 1 wherein determining and setting CAS latency compensation independently for each byte lane and parallelly among the plurality of byte lanes further comprises for each of the plurality of byte lanes independently and in parallel:
reading a known data pattern previously saved or located in one or more memory devices connected to the memory interface circuit;
iteratively capturing read data from the one or more memory devices at different CAS latency compensation control settings;
when for one of the plurality of byte lanes, the captured read data matches an expected read data value at a specific CAS latency compensation control setting, recording the specific CAS latency compensation control setting as an optimum CAS latency compensation control setting for that byte lane; and
programming control settings that produced the optimum CAS latency compensation for the byte lane into one or more control registers in the memory interface circuit.
8. The memory interface circuit of claim 7 , wherein iteratively capturing read data from the one or more memory devices at different CAS latency compensation control settings is performed by varying CAS latency compensation delay settings from a minimum to a maximum CAS latency compensation delay setting.
9. The memory interface circuit of claim 7 , wherein when the known data pattern is previously saved or located in the one or more memory devices connected to the memory interface circuit, application data contained in the one or more memory devices is temporarily moved to one or more different locations.
10. The memory interface circuit of claim 9 , wherein said one or more different locations includes at least one location contained within a host device containing the memory interface circuit wherein said one location is outside of the memory interface circuit.
11. The memory interface circuit of claim 1 , wherein one or more capture clocks capture read data received from one or more memory devices connected to the memory interface circuit, and wherein timing for the one or more capture clocks is controlled by said one or more controller circuits.
12. The memory interface circuit of claim 11 , wherein the memory interface circuit is contained within a host device and wherein the one or more capture clocks are derived from one or more core clocks originating within the host device.
13. A memory interface circuit for read operations, comprising:
one or more controller circuits for controlling the memory interface circuit;
one or more read data delay circuits for providing CAS latency compensation for a plurality of byte lanes by programmably delaying the read data for each byte lane in response to control settings; and
wherein the control settings for one or more read data delay circuits for providing CAS latency compensation for the plurality of byte lanes are determined and set independently for each byte lane and parallelly among the plurality of byte lanes.
14. The memory interface circuit of claim 13 , further comprising:
an expected read data memory designated for storing expected read data values; and
wherein determining control settings for the one or more read data delay circuits for providing CAS latency compensation, includes:
iteratively capturing read data from one or more memory devices connected to the memory interface circuit at different CAS latency compensation control settings; and
comparing the iteratively captured read data with expected read data values.
15. The memory interface circuit of claim 14 , further comprising:
wherein for a particular byte lane, when the captured read data matches an expected read data value at a specific CAS latency compensation control setting, the specific CAS latency compensation control setting is recorded as an optimum CAS latency compensation control setting for that byte lane.
16. The memory interface circuit of claim 14 , wherein the memory for storing expected read data values is located within a host device containing the memory interface circuit.
17. The memory interface circuit of claim 14 , wherein the one or more read data delay circuits for providing CAS latency compensation comprise at least two or more clocked storage elements.
18. The memory interface circuit of claim 17 , wherein a plurality of clocked storage elements among the at least two or more clocked storage elements are in series.
19. The memory interface circuit of claim 18 , wherein the one or more read data delay circuits for providing CAS latency compensation delay read data by variable numbers of clock edges according to an optimum CAS latency compensation control setting for that byte lane.