IP Library Granted Patent US 8,993,377
Granted Patent B2
US 8,993,377 · App. 13/231,839 · Granted Mar 31, 2015

Semiconductor device and method of bonding different size semiconductor die at the wafer level

Inventors: Jun Mo Koo (Singapore, SG); Pandi C. Marimuthu (Singapore, SG); Seung Wook Yoon (Singapore, SG); Il Kwon Shim (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
H01L24/96H01L21/561H01L21/563H01L21/565H01L21/568H01L21/6835H01L21/76898H01L23/3107H01L23/3128H01L24/03H01L24/05H01L24/11H01L24/13H01L24/16H01L24/17H01L24/19H01L24/20H01L24/29H01L24/32H01L24/81H01L24/82H01L24/95H01L25/0657H01L25/105H01L2221/68327H01L2221/68381H01L2221/68386H01L2224/0231H01L2224/02313H01L2224/02317H01L2224/02372H01L2224/02381H01L2224/0239H01L2224/024H01L2224/0345H01L2224/03452H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/04042H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/06131H01L2224/1132H01L2224/11334H01L2224/1134H01L2224/1145H01L2224/11462H01L2224/11464H01L2224/11849H01L2224/11901H01L2224/12105H01L2224/13025H01L2224/131H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/1403H01L2224/14181H01L2224/16146H01L2224/1703H01L2224/17181H01L2224/21H01L2224/2105H01L2224/215H01L2224/22H01L2224/221H01L2224/29144H01L2224/2919H01L2224/48105H01L2224/48175H01L2224/48228H01L2224/73204H01L2224/73265H01L2224/81005H01L2224/81815H01L2224/831H01L2224/95001H01L2224/96H01L2225/06513H01L2225/06541H01L2225/1052H01L2225/1058H01L2924/01004H01L2924/01013H01L2924/01029H01L2924/01047H01L2924/01049H01L2924/01073H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/014H01L2924/1205H01L2924/1206H01L2924/1207H01L2924/1433H01L2924/14335H01L2924/1434H01L2924/15311H01L2924/15331H01L2924/01006H01L2924/0105H01L2924/01074H01L2924/01322H01L2924/13091H01L2924/3511H01L24/97H01L2224/48227H01L2924/00H01L24/06H01L2924/12041H01L2924/1306
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Quick Facts
Patent No.
US 8,993,377
App. No.
13/231,839
Granted
Mar 31, 2015
Kind
B2
Abstract

A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.

Claims (71)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including an active surface and a second surface opposite the active surface;

forming a plurality of conductive vias partially through the active surface of the semiconductor wafer;

singulating the semiconductor wafer to separate a first semiconductor die;

disposing a second semiconductor die over the first semiconductor die with the active surface oriented toward the second semiconductor die;

depositing an encapsulant over and around the first and second semiconductor dies;

removing a portion of the second surface to expose a surface of the conductive vias coplanar with the second surface and the encapsulant; and

forming an interconnect structure over the first semiconductor die opposite the second semiconductor die, the interconnect structure including a first insulating layer and a first conductive layer.

2. The method of claim 1 , wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die.

3. The method of claim 1 , further including:

forming a second conductive layer over the active surface of the first semiconductor die prior to mounting the second semiconductor die, the second conductive layer being electrically connected to the conductive vias; and

forming a second insulating layer over the active surface of the first semiconductor die.

4. The method of claim 1 , further including depositing a mold underfill material between the first semiconductor die and second semiconductor die.

5. The method of claim 1 , wherein the second semiconductor die includes a memory device.

6. The method of claim 1 , further including stacking a plurality of second semiconductor die over the first semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a first semiconductor die including an active surface and second surface;

forming a plurality of conductive vias through the active surface of the first semiconductor die;

forming a first interconnect structure over the active surface of the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die with the first interconnect structure between the first and second semiconductor dies, the second semiconductor die extending outside a footprint of the first semiconductor die; and

depositing an encapsulant around the first and second semiconductor dies.

8. The method of claim 7 , further including

forming a second interconnect structure including an insulating layer and conductive layer over the first semiconductor die opposite the second semiconductor die.

9. The method of claim 7 , further including:

disposing the first semiconductor die over a carrier;

forming the plurality of conductive vias partially through the active surface of the first semiconductor die;

removing the carrier; and

removing a portion of the second surface of the first semiconductor die opposite the active surface of the first semiconductor die to expose the conductive vias.

10. The method of claim 7 , wherein the first interconnect structure includes an insulating layer and conductive layer, the conductive layer being electrically connected to the conductive vias.

11. The method of claim 7 , further including depositing a mold underfill material between the first semiconductor die and second semiconductor die.

12. The method of claim 7 , further including stacking a plurality of second semiconductor die over the first semiconductor die.

13. The method of claim 7 , further including forming a plurality of conductive vias through the encapsulant.

14. The method of claim 7 , wherein a footprint of the semiconductor die is larger than a footprint of the substrate.

15. A method of making a semiconductor device, comprising:

providing a first semiconductor die including an active surface and second surface;

forming a plurality of conductive vias through the active surface of the first semiconductor die and coplanar with the active surface of the first semiconductor die;

depositing a first encapsulant over the first semiconductor die including on the active surface;

forming an interconnect structure over the second surface of the first semiconductor die, the interconnect structure including a first insulating layer and a first conductive layer;

disposing a second semiconductor die over the first semiconductor die opposite the active surface with the interconnect structure between the first and second semiconductor dies;

depositing a second encapsulant over the second semiconductor die; and

removing a portion of the first encapsulant on the active surface of the first semiconductor die.

16. The method of claim 15 , wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die.

17. The method of claim 15 , wherein the second semiconductor die includes a memory device.

18. The method of claim 15 , further including depositing a mold underfill material between the first semiconductor die and second semiconductor die.

19. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of conductive vias formed through the substrate;

forming an interconnect structure over the substrate, the interconnect structure including a first insulating layer and a first conductive layer;

depositing a first encapsulant around the substrate and interconnect structure;

disposing a semiconductor die over the substrate with the interconnect structure between the substrate and semiconductor die; and

depositing a second encapsulant over the semiconductor die after disposing the semiconductor die over the substrate.

20. The method of claim 19 , further including:

forming the plurality of conductive vias partially through the substrate; and

removing a portion of the substrate to expose the conductive vias.

21. The method of claim 19 , wherein the substrate includes an active surface.

22. The method of claim 19 , further including depositing a mold underfill material between the substrate and semiconductor die.

23. A method of making a semiconductor device, comprising:

providing a substrate;

forming an interconnect structure over the substrate by,

(a) forming a first insulating layer over the substrate, and

(b) forming a first conductive layer over the substrate;

depositing a first encapsulant over the substrate and interconnect structure;

disposing a semiconductor die over the substrate with the interconnect structure between the substrate and semiconductor die; and

depositing a second encapsulant over the semiconductor die after disposing the semiconductor die over the substrate.

24. The method of claim 23 , further including:

forming a plurality of conductive vias through the substrate.

25. The method of claim 24 , further including:

forming a second conductive layer over the conductive vias; and

forming a second insulating layer over the second conductive layer.

26. The method of claim 23 , further including depositing a mold underfill material between the semiconductor die and the first insulating layer.

27. The method of claim 23 , wherein a footprint of the semiconductor die extends outside a footprint of the substrate.

28. The method of claim 23 , wherein the substrate includes an active surface.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0145. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0145 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2011
From: KOO, JUN MO; MARIMUTHU, PANDI C.; YOON, SEUNG WOOK; SHIM, IL KWON
To: STATS CHIPPAC, LTD.
Reel/Frame 027024/0545 →
Continuity (2)
Provisional Application 61387595 · Sep 29, 2010
Related Publication 20120074587A1 · Mar 29, 2012