Patent Assignment
Reel/Frame 038378/0145
Change of Name
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Properties
(60)
Semiconductor Device and Method of Making Wafer Level Chip Scale Package
Application:
14/449,914 →
Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
Application:
14/043,751 →
Semiconductor Device Having Balanced Band-Pass Filter Implemented with Lc Resonators
Application:
14/018,282 →
Integrated Circuit Packaging System with Trenched Leadframe and Method of Manufacture Thereof
Application:
13/934,797 →
Methods of Forming Solder Balls in Semiconductor Packages
Application:
13/931,295 →
Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
Application:
13/931,397 →
Method of Forming Rdl Wider Than Contact Pad Along First Axis and Narrower Than Contact Pad Along Second
Application:
13/893,616 →
Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
Application:
13/887,180 →
Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material
Application:
13/760,187 →
Integrated Circuit Packaging System with Coreless Substrate and Method of Manufacture Thereof
Application:
13/742,580 →
Integrated Circuit Packaging System with Molded Grid-Array Mechanism and Method of Manufacture Thereof
Application:
13/740,151 →
Package Structure and Manufacturing Method Thereof
Application:
13/590,197 →
Semiconductor Device and Method of Forming RF Balun having Reduced Capacitive Coupling and High CMRR
Application:
13/571,068 →
Integrated Circuit Package System with Internal Stacking Module
Application:
13/563,598 →
Integrated Circuit Packaging System with Thermal Structures and Method of Manufacture Thereof
Application:
13/528,051 →
Semiconductor Device and Method of Forming Thermally Conductive Layer Between Semiconductor Die and Build-Up Interconnect Structure
Application:
13/492,687 →
Integrated Circuit Package with Molded Cavity
Application:
13/463,148 →
Integrated Circuit Package System with Post-Passivation Interconnection and Integration
Application:
13/456,145 →
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
Application:
13/423,262 →
Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die
Application:
13/349,510 →
Integrated Circuit Packaging System with Perimeter Antiwarpage Structure and Method of Manufacture Thereof
Application:
13/327,651 →
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
Application:
13/312,730 →
Semiconductor Device with Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids
Application:
13/303,019 →
Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe with Base Leads and Embedded Semiconductor Die
Application:
13/284,811 →
Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
Application:
13/273,537 →
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
Application:
13/248,312 →
Integrated Circuit Packaging System with Heat Shield and Method of Manufacture Thereof
Application:
13/244,273 →
Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
Application:
13/231,839 →
Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
Application:
13/181,838 →
Wafer Level Die Integration and Method Therefor
Application:
13/170,116 →
Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps
Application:
13/167,133 →
Integrated Circuit Packaging System with Vertical Interconnects and Method of Manufacture Thereof
Application:
13/167,631 →
Integrated Circuit Packaging System with a Lead and Method of Manufacture Thereof
Application:
13/167,458 →
Integrated Circuit Packaging System with Thermal Emission and Method of Manufacture Thereof
Application:
13/166,809 →
Semiconductor Device Having Ipd Structure with Smooth Conductive Layer and Bottom-Side Conductive Layer
Application:
13/090,590 →
Etched Recess Package on Package System
Application:
13/080,469 →
Integrated Circuit Packaging System for Electromagnetic Interference Shielding and Method of Manufacture Thereof
Application:
13/072,603 →
Integrated Circuit Packaging System with a Flip Chip and Method of Manufacture Thereof
Application:
13/052,816 →
Integrated Circuit Packaging System Having Planar Interconnect and Method for Manufacture Thereof
Application:
13/041,869 →
Integrated Circuit Packaging System with Embedded Circuitry and Post
Application:
13/023,293 →
System and Method for Directional Grinding on Backside of a Semiconductor Wafer
Application:
13/005,666 →
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
Application:
12/969,467 →
Semiconductor Device and Method of Forming Recesses in Substrate for Same Size or Different Sized Die with Vertical Integration
Application:
12/964,117 →
Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support
Application:
12/775,170 →
Integrated Circuit Packaging System with Interconnect and Method of Manufacture Thereof
Application:
12/731,045 →
Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of Wlcsp
Application:
12/724,354 →
Semiconductor Device and Method of Forming Recessed Conductive Vias in Saw Streets
Application:
12/719,398 →
Semiconductor Multi-Package Module Including Tape Substrate Land Grid Array Package Stacked Over Ball Grid Array Package
Application:
12/511,012 →
Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test
Application:
12/467,094 →
Semiconductor Device and Method of Forming Topside and Bottom-Side Interconnect Structures Around Core Die with Tsv
Application:
12/332,835 →
Integrated Circuit Package System with Support Carrier and Method of Manufacture Thereof
Application:
12/273,544 →
Integrated Circuit Package System with Relief
Application:
12/123,995 →
Integrated Circuit Package-in-Package System Housing a Plurality of Stacked and Offset Integrated Circuits and Method of Manufacture Therefor
Application:
11/951,958 →
Integrated Circuit Package System with Array of External Interconnects
Application:
11/936,516 →
Integrated Circuit Package System with Overhang Die
Application:
11/768,790 →
Integrated Circuit Package System with Device Cavity
Application:
11/744,062 →
Integrated Circuit Package System with Molded Strip Protrusion
Application:
11/689,317 →
Integrated Circuit Package System with Heat Sink
Application:
11/558,413 →
Stacked Die Package System
Application:
11/164,160 →
Integrated, Integrated Circuit Singulation System
Application:
11/162,622 →