Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
View Patent ↗A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.
1. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant disposed over and around the first semiconductor die;
a plurality of conductive pillars formed through the encapsulant and disposed around the first semiconductor die;
a first stepped interconnect structure formed over a first surface of the encapsulant and electrically connected to the conductive pillars;
a second semiconductor die disposed within an opening in the first stepped interconnect structure;
a third semiconductor die disposed over the first stepped interconnect structure and second semiconductor die;
an interconnect structure formed over the first semiconductor die and a second surface of the encapsulant and electrically connected to the conductive pillars; and
wherein a surface of the first semiconductor die is devoid of encapsulant.
2. The semiconductor device of claim 1 , further including:
a second stepped interconnect structure formed over the first stepped interconnect structure, wherein the third semiconductor die is disposed within an opening in the second stepped interconnect structure; and
a fourth semiconductor die disposed over the second stepped interconnect structure.
3. The semiconductor device of claim 1 , wherein the opening in the first stepped interconnect structure is disposed over the first semiconductor die.
4. The semiconductor device of claim 1 , further including a coating disposed between the third semiconductor die and the second semiconductor die.
5. The semiconductor device of claim 1 , further including:
a conductive layer formed over a portion of the first surface of the encapsulant; and
an insulating layer formed on a portion of the conductive layer.
6. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant disposed around the first semiconductor die;
a plurality of conductive pillars formed through the encapsulant and disposed around the first semiconductor die;
a first stepped interconnect structure formed over a first surface of the encapsulant and electrically connected to the conductive pillars;
a second semiconductor die disposed within an opening in the first stepped interconnect structure;
a third semiconductor die disposed over the first stepped interconnect structure; and
an interconnect structure formed over the first semiconductor die and a second surface of the encapsulant and electrically connected to the conductive pillars.
7. The semiconductor device of claim 6 , further including:
a second stepped interconnect structure formed over the first stepped interconnect structure, wherein the third semiconductor die is disposed within an opening in the second stepped interconnect structure; and
a fourth semiconductor die disposed over the second stepped interconnect structure.
8. The semiconductor device of claim 6 , further including:
a through silicon via formed in the first semiconductor die; and
a conductive layer formed over a portion of the first semiconductor die and first surface of the encapsulant and electrically connected to the through silicon via.
9. The semiconductor device of claim 6 , further including an insulative layer formed on a portion of the first semiconductor die and first surface of the encapsulant.
10. The semiconductor device of claim 6 , further including a coating disposed between the third semiconductor die and the second semiconductor die.
11. The semiconductor device of claim 6 , further including:
a conductive layer formed over a portion of the first semiconductor die and first surface of the encapsulant; and
an insulating layer formed on a portion of the conductive layer.
12. The semiconductor device of claim 6 , wherein the first stepped interconnect structure includes a pre-formed substrate.
13. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant disposed around the first semiconductor die;
a plurality of conductive pillars formed through the encapsulant and disposed around the first semiconductor die;
a first stepped interconnect structure formed over a surface of the encapsulant;
a second semiconductor die disposed within an opening in the first stepped interconnect structure; and
wherein a surface of the first semiconductor die is devoid of encapsulant.
14. The semiconductor device of claim 13 , further including a third semiconductor die disposed over the first stepped interconnect structure.
15. The semiconductor device of claim 13 , further including:
a second stepped interconnect structure formed over the first stepped interconnect structure;
a third semiconductor die disposed within an opening in the second stepped interconnect structure; and
a fourth semiconductor die disposed over the second stepped interconnect structure.
16. The semiconductor device of claim 13 , wherein the second semiconductor die is partially outside the opening in the first stepped interconnect structure.
17. The semiconductor device of claim 13 , further including a conductive layer formed on a surface of the first semiconductor die.
18. The semiconductor device of claim 17 , further including a through silicon via formed in the first semiconductor die and electrically connected to the conductive layer.
19. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant disposed around the first semiconductor die;
a plurality of conductive pillars formed through the encapsulant and disposed around the first semiconductor die;
a first stepped interconnect structure formed over a first surface of the encapsulant;
a second semiconductor die disposed within an opening in the first stepped interconnect structure; and
a third semiconductor die disposed over the first stepped interconnect structure.
20. The semiconductor device of claim 19 , wherein the second semiconductor die is disposed partially outside the opening in the first stepped interconnect structure.
21. The semiconductor device of claim 19 , further including a conductive layer formed on the first semiconductor die and a second surface of the encapsulant and electrically connected to the first semiconductor die and conductive pillars.
22. The semiconductor device of claim 19 , further including a conductive layer formed over the first semiconductor die and first surface of the encapsulant.
23. The semiconductor device of claim 22 , further including an insulating layer formed over a portion of the conductive layer.
24. The semiconductor device of claim 19 , further including:
a second stepped interconnect structure formed over the first stepped interconnect structure, wherein the third semiconductor die is disposed within an opening in the second stepped interconnect structure; and
a fourth semiconductor die disposed over the second stepped interconnect structure.
25. The semiconductor device of claim 19 , wherein the second semiconductor die is disposed over the first semiconductor die.
26. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant disposed around the first semiconductor die;
a first stepped interconnect structure formed over a first surface of the encapsulant; and
an opening in the first stepped interconnect structure.
27. The semiconductor device of claim 26 , further including a second semiconductor die disposed within the opening in the first stepped interconnect structure.
28. The semiconductor device of claim 26 , further including a second stepped interconnect structure formed over the first stepped interconnect structure.
29. The semiconductor device of claim 28 , further including:
a second semiconductor die disposed within the opening in the first stepped interconnect structure; and
a third semiconductor die disposed within an opening in the second stepped interconnect structure.
30. The semiconductor device of claim 26 , wherein the first stepped interconnect structure includes a pre-formed substrate.