Integrated circuit package-in-package system housing a plurality of stacked and offset integrated circuits and method of manufacture therefor

1. An integrated circuit package-in-package system comprising:

a die-attach paddle having a first edge and a second edge, wherein the second die is opposite the first edge;

first integrated circuits mounted over the die-attach paddle, the first integrated circuits having:

(a) a first component having a first border and a second border opposite the first border,

(b) a second component coupled to the first component, the second component having a third border and a fourth border opposite the third border,

wherein the first component and the second component are stacked in a first offset configuration,

wherein the first border and the third border each faces the first edge and wherein the second border and the fourth border each faces the second edge, and

wherein the first border is closer to the first edge than the third border and the fourth border closer to the second edge than the second border;

a second edge lead adjacent to the second edge, wherein the second edge lead is connected to the first integrated circuits;

an integrated circuit package system having an inner encapsulation covering second integrated circuits, the integrated circuit package system is mounted below and to the die-attach paddle, wherein the second integrated circuit includes:

(a) a third component having a fifth border and a sixth border opposite the fifth border,

(b) a fourth component coupled to the third component, the fourth component having a seventh border and an eighth border opposite the seventh border,

wherein the third component and the fourth component are stacked in a second offset configuration, the second offset configuration different from the first offset configuration,

wherein the fifth border and the seventh border each faces the first edge and wherein the sixth border and the eighth border each faces the second edge,

wherein the seventh border is closer to the first edge than the fifth border and the sixth border is closer to the second edge than the eighth border,

wherein the third border is closer to the first edge than both the fifth border and the seventh border, and

wherein the sixth border is closer to the second edge than the second border, the fourth border, and the eighth border;

a first edge lead adjacent to the first edge, wherein the first edge lead is connected to the second integrated circuits; and

a package encapsulation covering the first integrated circuits, the integrated circuit package system, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed, with a boundary portion between the inner encapsulation and the package encapsulation separating the inner encapsulation from the package encapsulation, and wherein the first offset configuration and the second offset configuration collectively provide a more balanced weight distribution of the first integrated circuits and the second integrated circuits within the package encapsulation.

2. The system as claimed in claim 1 further comprising a first encapsulation covering the first integrated circuits.

3. The system as claimed in claim 1 further comprising the first integrated circuits connected to the first edge lead.

4. The system as claimed in claim 1 further comprising the second integrated circuits connected to the second edge lead.

5. The system as claimed in claim 1 wherein:

the inner encapsulation covering the second integrated circuits, partially exposing a first external contact from the inner encapsulation; and

further comprising:

a first electrical interconnect connects between the first external contact and the first edge lead.

6. The system as claimed in claim 5 further comprising a second electrical interconnect connecting the second integrated circuits to the first external contact.

7. The system as claimed in claim 5 further comprising:

a first encapsulation covering the first integrated circuits; and

a second external contact partially exposed by the first encapsulation connected to the first integrated circuits.

8. The system as claimed in claim 5 further comprising:

a second external contact partially exposed by the inner encapsulation; and

a second electrical interconnect connecting the second external contact and the second edge lead.

9. The system as claimed in claim 5 wherein:

one of the first integrated circuits is further connected to the first edge lead; and

one of the second integrated circuits is further connected to the second edge lead.