Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration
View Patent ↗A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer;
forming a contact pad over a surface of the semiconductor wafer;
forming a first insulating layer over the surface of the semiconductor wafer;
forming a redistribution layer over the first insulating layer and contact pad, the redistribution layer including a plurality of bump formation areas;
forming a second insulating layer over the first insulating layer and redistribution layer;
forming a plurality of openings in the second insulating layer to expose quadrants of the bump formation areas while leaving a portion of the second insulating layer within a central region of the bump formation areas to define the quadrants;
forming an under bump metallization (UBM) layer over the openings in the second insulating layer in the bump formation areas electrically connected to the redistribution layer; and
forming a bump over the UBM layer in the bump formation areas.
2. The method of claim 1 , wherein the openings in the second insulating layer are separated by a continuous portion of the second insulating layer.
3. The method of claim 1 , wherein the openings in the second insulating layer in the bump formation areas occupy less than the entire bump formation areas.
4. The method of claim 1 , wherein the openings in the second insulating layer in the bump formation areas occupy 60 percent of the bump formation areas.
5. The method of claim 1 , wherein the openings in the second insulating layer in the bump formation areas reduce adverse effects of electro-migration of the redistribution layer.
6. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a redistribution layer over the semiconductor die, the redistribution layer including an interconnect formation area;
forming a first insulating layer over the redistribution layer;
forming a plurality of openings in the first insulating layer in the interconnect formation area while leaving a continuous portion of the first insulating layer extending across the interconnect formation area;
forming an under bump metallization (UBM) layer over the openings in the first insulating layer in the interconnect formation area electrically connected to the redistribution layer; and
forming a plurality of bumps over the semiconductor die, a first bump of the plurality of bumps covering the plurality of openings in the first insulating layer and covering the continuous portion of the first insulating layer within the interconnect formation area.
7. The method of claim 6 , further including forming the first bump over the UBM layer.
8. The method of claim 6 , further including forming a first conductive layer over a surface of the semiconductor die prior to forming the redistribution layer.
9. The method of claim 6 , further including forming at least two openings in the first insulating layer in the interconnect formation area to expose the redistribution layer, the at least two openings being separated by the continuous portion of the first insulating layer.
10. The method of claim 6 , wherein the openings in the first insulating layer in the interconnect formation area occupy less than the entire interconnect formation area.
11. The method of claim 6 , wherein the openings in the first insulating layer in the interconnect formation area occupy 60 percent of the interconnect formation area.
12. The method of claim 6 , wherein the openings in the first insulating layer in the interconnect formation area reduce adverse effects of electro-migration.
13. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first conductive layer over the semiconductor die, the first conductive layer including an interconnect formation area;
forming a first insulating layer over the first conductive layer;
forming a first opening and a second opening in the first insulating layer in the interconnect formation area of the first conductive layer; and
forming a plurality of interconnect structures over the semiconductor die, wherein a first interconnect structure of the plurality of interconnect structures is disposed over the first and second openings in the first insulating layer in the interconnect formation area.
14. The method of claim 13 , further including forming a second conductive layer over the first and second openings in the first insulating layer prior to forming the interconnect structures.
15. The method of claim 13 , wherein forming the interconnect structure includes forming a bump over the semiconductor die.
16. The method of claim 13 , further including:
forming a second conductive layer over a surface of the semiconductor die prior to forming the first conductive layer; and
forming a second insulating layer over the surface of the semiconductor die and second conductive layer.
17. The method of claim 13 , wherein the first and second openings are separated by portions of the first insulating layer.
18. The method of claim 13 , wherein the first and second openings in the first insulating layer in the interconnect formation area occupy less than the entire interconnect formation area.
19. The method of claim 13 , wherein the first and second openings in the first insulating layer in the interconnect formation area reduce adverse effects of electro-migration.
20. A semiconductor device, comprising:
a semiconductor die;
a first conductive layer formed over a surface of the semiconductor die;
a first insulating layer formed over the first conductive layer;
a plurality of openings formed in the first insulating layer in an interconnect formation area of the first conductive layer; and
a discrete interconnect structure formed over the plurality of openings in the first insulating layer in the interconnect formation area electrically connected to the first conductive layer.
21. The semiconductor device of claim 20 , further including a second conductive layer formed over the openings.
22. The semiconductor device of claim 21 , wherein the discrete interconnect structure includes a bump formed over the second conductive layer.
23. The semiconductor device of claim 20 , further including at least two openings in the first insulating layer formed in the interconnect formation area to expose the first conductive layer, the at least two openings being separated by portions of the first insulating layer.
24. The semiconductor device of claim 20 , wherein the openings in the first insulating layer in the interconnect formation area occupy less than the entire interconnect formation area.