Integrated circuit packaging system with interconnect and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing an interposer having an interposer first side and an interposer second side opposing the interposer first side;

mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer;

connecting first interconnects between the active side and the interposer first side, the first interconnects are connected to integrated circuit pads and have a first density on the interposer first side, the integrated circuit pads have a pad pitch;

mounting the interposer over a package carrier with the interposer first side facing the package carrier;

connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density is approximately the same as the first density;

mounting an integrated circuit interconnect over the package carrier, the integrated circuit interconnect has a bump pitch, the pad pitch is three to four times tighter than the bump pitch, the integrated circuit has a higher input/output (I/O) density than that of the integrated circuit interconnect;

connecting the integrated circuit interconnect between the active side of the integrated circuit and the package carrier to provide a shorter electrical signal path between the integrated circuit and the package carrier than the first interconnects and the second interconnects; and

forming an encapsulation over the package carrier covering the interposer and the second interconnects.

2. The method as claimed in claim 1 wherein connecting the first interconnects includes connecting the first interconnects at an interposer peripheral region of the interposer.

3. The method as claimed in claim 1 wherein connecting the second interconnects includes connecting the second interconnects at an interposer peripheral region of the interposer.

4. The method as claimed in claim 1 wherein:

connecting the integrated circuit interconnect includes connecting the integrated circuit interconnect in an array configuration;

connecting the first interconnects between the active side and the interposer first side includes connecting the first interconnects to the integrated circuit peripheral region and the interposer first side; and

connecting the second interconnects having the second density at least three times greater than that of the integrated circuit interconnect.

5. The method as claimed in claim 1 wherein:

mounting the integrated circuit includes mounting the integrated circuit having an integrated circuit interior region, the integrated circuit interconnect at the integrated circuit interior region; and

connecting the first interconnects includes connecting the first interconnects adjacent to the integrated circuit interconnect.

6. The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation covering the integrated circuit interconnect and the first interconnects.

7. The method as claimed in claim 1 further comprising forming an underfill covering the integrated circuit interconnect and the first interconnects.

8. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting a high density flip chip to the interposer first side.

9. An integrated circuit packaging system comprising:

an interposer having an interposer first side and an interposer second side opposing the interposer first side;

an integrated circuit mounted to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer;

first interconnects between the active side and the interposer first side, the first interconnects are connected to integrated circuit pads and have a first density on the interposer first side, the integrated circuit pads have a pad pitch;

a package carrier with the interposer thereover, the interposer first side facing the package carrier;

second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density is approximately the same as the first density;

the integrated circuit having an integrated circuit interconnect, the integrated circuit interconnect having a bump pitch disposed between the active side of the integrated circuit and the package carrier, the pad pitch is three to four times tighter than the bump pitch, the integrated circuit has a higher input/output (I/O) density than that of the integrated circuit interconnect, the integrated circuit interconnect is configured to provide a shorter electrical signal path between the integrated circuit and the package carrier than the first interconnects and the second interconnects; and

an encapsulation over the package carrier covering the interposer and the second interconnects.

10. The system as claimed in claim 9 wherein the first interconnects are at an interposer peripheral region of the interposer.

11. The system as claimed in claim 9 wherein the second interconnects are at an interposer peripheral region of the interposer.

12. The system as claimed in claim 9 wherein:

the integrated circuit has an integrated circuit interconnect facing away from the interposer; and

the package carrier with the interposer thereover includes the integrated circuit interconnect mounted over the package carrier.

13. The system as claimed in claim 9 wherein:

the integrated circuit interconnect is in an array configuration;

the first interconnects between the active side and the interposer first side is connected to the integrated circuit peripheral region and the interposer first side; and

the second interconnects has the second density at least three times greater than that of the integrated circuit interconnect.

14. The system as claimed in claim 9 wherein:

the integrated circuit has an integrated circuit interior region, the integrated circuit interconnect at the integrated circuit interior region; and

the first interconnects are adjacent to the integrated circuit interconnect.

15. The system as claimed in claim 9 wherein the encapsulation covers the integrated circuit interconnect and the first interconnects.

16. The system as claimed in claim 9 further comprising an underfill covering the integrated circuit interconnect and the first interconnects.

17. The system as claimed in claim 9 wherein the integrated circuit is a high density flip chip mounted to the interposer first side.