IP Library Granted Patent US 8,956,914
Granted Patent B2
US 8,956,914 · App. 11/768,790 · Granted Feb 17, 2015

Integrated circuit package system with overhang die

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,956,914
App. No.
11/768,790
Granted
Feb 17, 2015
Kind
B2
Abstract

An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.

Claims (26)

1. A method of manufacturing an integrated circuit package system comprising:

forming a substrate having a solder mask with a support structure formed by only patterning the solder mask;

attaching a first integrated circuit device to the support structure;

connecting the substrate and the first integrated circuit device; and

encapsulating the first integrated circuit device and the support structure.

2. The method as claimed in claim 1 wherein mounting the second integrated circuit device includes mounting the second integrated circuit device adjacent to the support structure.

3. The method as claimed in claim 1 wherein mounting the second integrated circuit device within the cavity includes mounting the second integrated circuit device below the first integrated circuit device.

4. The method as claimed in claim 1 further comprising

connecting the second integrated circuit device to the substrate.

5. A method of manufacturing an integrated circuit package system comprising: forming a substrate having a solder mask with a support structure and a further support structure formed by only patterning the solder mask including etching the solder mask for forming the support structure and the further support structure; attaching a first integrated circuit device, having a first non-active side and a first active side, to the support structure with the first non-active side facing the support structure; mounting a second integrated circuit device, having a second non-active side with a first adhesive thereon, within a cavity between the support structure and the further support structure, and the first adhesive facing the substrate; connecting a trace in the substrate exposed by the support structure and the first active side; and encapsulating the first integrated circuit device, a first internal interconnect, the support structure, and the further support structure.

6. The method as claimed in claim 5 further comprising attaching a second adhesive to the first non-active side.

7. The method as claimed in claim 5 further comprising:

attaching a second adhesive to the first non-active side;

mounting the second integrated circuit device adjacent to the support structure; and

wherein attaching the first integrated circuit device over the support structure includes:

mounting the first integrated circuit device over the second integrated circuit device with the second adhesive facing the second integrated circuit device.

8. The method as claimed in claim 5 further comprising: attaching a second adhesive to the first non-active side; connecting an internal interconnect over the support structure between the second integrated circuit device and the substrate; and wherein attaching the first integrated circuit device to the support structure includes: mounting the first integrated circuit device over the second integrated circuit device with the internal interconnect in the second adhesive.

9. An integrated circuit package system comprising: a substrate having a solder mask with a support structure and a further support structure patterned from the solder mask; a first integrated circuit device attached to the support structure, the first integrated circuit device, includes a first non-active side and a first active side with the first non-active side facing the support structure, connected to the substrate; a second integrated circuit device, having a second non-active side with a first adhesive thereon and a second active side, within a cavity between the support structure and the further support structure, and the first adhesive facing the substrate; and a package encapsulation over the first integrated circuit device, the support structure, and the further support structure.

10. The system as claimed in claim 9 wherein the second integrated circuit device adjacent to the support structure.

11. The system as claimed in claim 9 wherein the second integrated circuit device within the cavity includes the second integrated circuit device below the first integrated circuit device.

12. The system as claimed in claim 9 wherein the second integrated circuit device adjacent to the support structure and connected to the substrate.

13. The system as claimed in claim 9 further comprising:

a trace in the substrate exposed by the support structure connected to the first active side.

14. The system as claimed in claim 13 further comprising a second adhesive attached to the first non-active side.

15. The system as claimed in claim 13 further comprising: a second adhesive attached to the first non-active side; and wherein the first integrated circuit device attached to the support structure includes: the first integrated circuit device over the second integrated circuit device with the second adhesive facing the second integrated circuit device.

16. The system as claimed in claim 13 further comprising: a second adhesive attached to the first non-active side; an internal interconnect over the support structure between the second integrated circuit device and the substrate; and wherein the first integrated circuit device attached to the support structure includes: the first integrated circuit device over the second integrated circuit device with the internal interconnect in the second adhesive.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0145. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0145 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2007
From: YUN, JA EUN; JU, JONG WOOK
To: STATS CHIPPAC LTD.
Reel/Frame 019638/0474 →