Granted Patent B2

US 8,975,980 · App. 14/018,282 · Granted Mar 10, 2015

Abstract

Claims (57)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first inductor over the substrate;

forming a second inductor over the substrate; and

forming a third inductor including a first end terminal of the third inductor oriented towards a second end terminal of the third inductor over the substrate around a perimeter of the first inductor and second inductor and non-overlapping and non-interleaving with the first inductor and second inductor to induce magnetic coupling between the first, second, and third inductors, wherein the first inductor is displaced off-center with respect to the second inductor.

2. The method of claim 1 , further including:

providing a first capacitor coupled between first and second end terminals of the first inductor; and

providing a second capacitor coupled between first and second end terminals of the second inductor.

3. The method of claim 1 , further including providing a capacitor coupled between the first and second end terminals of the third inductor.

4. The method of claim 1 , further including forming the first inductor adjacent to and non-overlapping with the second inductor.

5. The method of claim 1 , wherein the first inductor and second inductor are substantially coplanar.

6. The method of claim 1 , further including coupling the first inductor to a first unbalanced port and a second unbalanced port.

7. The method of claim 1 , further including coupling the second inductor to a first balanced port and a second balanced port.

8. A method of making a semiconductor device, comprising:

providing a first inductor;

providing a second inductor disposed adjacent to and displaced off-center from the first inductor; and

providing a third inductor including a first end terminal facing a second end terminal around a perimeter of the first inductor and non-overlapping and non-interleaving the second inductor to induce magnetic coupling between the first, second, and third inductors.

9. The method of claim 8 , wherein the first inductor and second inductor are substantially coplanar.

10. The method of claim 8 , further including:

providing a first capacitor coupled between first and second end terminals of the first inductor; and

providing a second capacitor coupled between first and second end terminals of the second inductor.

11. The method of claim 8 , further including providing a capacitor coupled between the first and second end terminals of the third inductor.

12. The method of claim 8 , further including forming the third inductor non-overlapping with the first inductor and second inductor.

13. The method of claim 8 , further including:

providing a substrate;

forming the first inductor over the substrate;

forming the second inductor over the substrate; and

forming the third inductor over the substrate.

14. The method of claim 8 , further including coupling the first inductor to a first unbalanced port and a second unbalanced port.

15. The method of claim 8 , further including coupling the second inductor to a first balanced port and a second balanced port.

16. A semiconductor device, comprising:

a substrate;

a first inductor formed over the substrate;

a second inductor formed over the substrate and oriented different from the first inductor; and

a third inductor formed around and non-overlapping and non-interleaving the first inductor to induce magnetic coupling between the first, second, and third inductors.

17. The semiconductor device of claim 16 , further including:

a first capacitor coupled between first and second end terminals of the first inductor; and

a second capacitor coupled between first and second end terminals of the second inductor.

18. The semiconductor device of claim 16 , further including a capacitor coupled between first and second end terminals of the third inductor.

19. The semiconductor device of claim 16 , wherein the first inductor is disposed adjacent to and non-overlapping with the second inductor.

20. The semiconductor device of claim 16 , wherein the third inductor is disposed non-overlapping with the first inductor and second inductor.

21. The semiconductor device of claim 16 , wherein the first inductor and second inductor are substantially coplanar.

22. The semiconductor device of claim 16 , further including a first unbalanced port and a second unbalanced port coupled to the first inductor.

23. The semiconductor device of claim 16 , further including a first unbalanced port and a second unbalanced port coupled to the second inductor.

24. A semiconductor device, comprising:

a first inductor;

a second inductor disposed adjacent to and displaced off-center with the first inductor; and

a third inductor disposed around and outside and non-overlapping and non-interleaving the first inductor and second inductor to induce magnetic coupling between the first, second, and third inductors.

25. The semiconductor device of claim 24 , wherein the first inductor and second inductor are substantially coplanar.

26. The semiconductor device of claim 24 , further including:

a first capacitor coupled between first and second end terminals of the first inductor;

a second capacitor coupled between first and second end terminals of the second inductor; and

a third capacitor coupled between first and second end terminals of the third inductor.

27. The semiconductor device of claim 24 , wherein the first inductor and second inductor are formed with 8 μm conductive material.

28. The semiconductor device of claim 24 , further including a substrate, wherein the first inductor, second inductor, and third inductor are formed over the substrate.

29. The semiconductor device of claim 24 , further including a first unbalanced port and a second unbalanced port coupled to the first inductor.

30. The semiconductor device of claim 24 , further including a first unbalanced port and a second unbalanced port coupled to the second inductor.

Assignments (9)