Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof
View Patent ↗A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region;
forming an insulation cover on the lead-frame and on the metal connector;
connecting an integrated circuit die over the insulation cover;
forming a top encapsulation on the integrated circuit die with the peripheral mounting region laterally adjacent to the top encapsulation;
forming a routing layer, having a conductive land, from the lead-frame; and
forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
2. The method as claimed in claim 1 wherein forming the top encapsulation includes forming the top encapsulation with a top chip surface of the integrated circuit die exposed from the top encapsulation.
3. The method as claimed in claim 1 wherein forming the bottom encapsulation includes forming the bottom encapsulation encapsulating a lateral edge of the metal connector.
4. The method as claimed in claim 1 further comprising:
mounting a further die on the integrated circuit die; and
wherein:
forming the top encapsulation includes forming the top encapsulation on the further die.
5. The method as claimed in claim 1 further comprising mounting a stacked package, having a stack interconnect, over the top encapsulation, the stack interconnect mounted to the metal connector.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region;
forming an insulation cover on the lead-frame and on the metal connector;
connecting an integrated circuit die over the insulation cover;
forming an under-fill between the integrated circuit die and the insulation cover;
forming a top encapsulation on the integrated circuit die with the peripheral mounting region laterally adjacent to the top encapsulation;
forming a routing layer, having a conductive land, from the lead-frame; and
forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
7. The method as claimed in claim 6 further comprising forming a connection opening in the insulation cover for exposing a portion of the metal connector.
8. The method as claimed in claim 6 wherein forming the bottom encapsulation includes forming the bottom encapsulation coplanar to a bottom cover of the conductive land.
9. The method as claimed in claim 6 wherein forming the bottom encapsulation includes forming the bottom encapsulation isolated from the top encapsulation.
10. The method as claimed in claim 6 wherein connecting the integrated circuit die includes connecting a flip chip.
11. An integrated circuit packaging system comprising:
a routing layer having a conductive land, a metal connector, and a peripheral mounting region, the metal connector on the conductive land;
an insulation cover on the routing layer;
an integrated circuit die mounted over the insulation cover;
a top encapsulation encapsulating the integrated circuit die with the peripheral mounting region laterally adjacent to the top encapsulation; and
a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
12. The system as claimed in claim 11 wherein the integrated circuit die includes a top chip surface exposed from the top encapsulation.
13. The system as claimed in claim 11 wherein the bottom encapsulation encapsulates a lateral edge of the metal connector.
14. The system as claimed in claim 11 further comprising:
a further die mounted on the integrated circuit die; and
wherein:
the top encapsulation encapsulates the further die.
15. The system as claimed in claim 11 further comprising a stacked package, having a stacked interconnect, over the top encapsulation, the stack interconnect mounted to the metal connector.
16. The system as claimed in claim 11 further comprising an under-fill between the integrated circuit die and the insulation cover.
17. The system as claimed in claim 16 wherein the insulation cover includes a connection opening for exposing a portion of the metal connector.
18. The system as claimed in claim 16 wherein the bottom encapsulation is coplanar with a bottom cover of the conductive land.
19. The system as claimed in claim 16 wherein the bottom encapsulation is isolated from the top encapsulation.
20. The system as claimed in claim 16 wherein the integrated circuit die is a flip chip.