Low interfacial defect field effect transistor
A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.
1. A semiconductor structure comprising:
a semiconductor fin comprising a first semiconductor material, said semiconductor fin comprising a source region located on a source-side buffer material portion that is in contact with a portion of a substrate, a drain region located on a drain-side buffer material portion that is in contact with another portion of said substrate, and a body region laterally contacting said source region and said drain region and vertically spaced from said substrate; and
a cap layer comprising a second semiconductor material and contacting a top surface, a bottom surface and a pair of sidewalls of said body region, a sidewall of said source-side buffer material region and a sidewall of said drain-side buffer material region, wherein a horizontal interface between said source region and said source-side buffer material portion, a horizontal interface between said drain region, and said drain-side buffer material portion and a horizontal interface between said bottom surface of said body region and said cap layer are within a same horizontal plane.
2. The semiconductor structure of claim 1 , wherein a pair of vertical interfaces between said semiconductor fin and said cap layer are within a pair of vertical planes spaced by a width of said semiconductor fin.
3. The semiconductor structure of claim 1 , wherein each of said first and second semiconductor materials is single crystalline and epitaxially aligned to each other.
4. The semiconductor structure of claim 1 , further comprising a dielectric material layer in contact with said source region, said drain region, said source-side buffer material portion, and said drain-side buffer material portion, wherein vertical interfaces between said source region and said dielectric material layer, vertical interfaces between said drain region and said dielectric material layer, vertical interfaces between said source-side buffer material portion and said dielectric material layer, vertical interfaces between said drain-side buffer material portion and said dielectric material layer, and vertical interfaces between said body region and said cap layer are within a pair of vertical planes.
5. The semiconductor structure of claim 1 , further comprising:
a raised source region in contact with a top surface and sidewall surfaces of said source region and sidewall surface of said source-side buffer material portion; and
a raised drain region in contact with a top surface and sidewalls of said drain region and sidewall surface of said drain-side buffer material portion, wherein a horizontal interface between said source region and said raised source region and a horizontal interface between said drain region and said raised drain region are within said same horizontal plane.
6. The semiconductor structure of claim 4 , wherein a horizontal interface between said source region and said dielectric material layer and a horizontal interface between said drain region and said dielectric material layer are within said same horizontal plane.
7. The semiconductor structure of claim 1 , wherein said cap layer has a first type strain, and said semiconductor fin has second type strain that is the opposite of said first type strain, and said first type strain and said second type strain include a compressive strain and a tensile strain.
8. The semiconductor structure of claim 1 , wherein said semiconductor fin, said source-side buffer material portion, and said drain-side buffer material portion have a same width.
9. The semiconductor structure of claim 1 , wherein said body region is vertically spaced from said substrate by a distance that is equal to a height of each of said source-side buffer material portion and said drain-side buffer material portion.
10. The semiconductor structure of claim 1 , wherein said source region has a first length and said source-side buffer material portion has a second length less than said first length, and wherein said drain region has a third length and said drain-side buffer material portion has a fourth length less than said third length.
11. The semiconductor structure of claim 10 , wherein said cap layer contacts a portion of a bottom surface of said source region and a portion of a bottom surface of said drain region.
12. The semiconductor structure of claim 1 , wherein each of said source-side buffer material portion and said drain-side buffer material portion is composed of a third semiconductor material different from said first semiconductor material.
13. The semiconductor structure of claim 12 , wherein said body region has a doping of a first conductivity type, and each of said source-side buffer material portion, said drain-side buffer material portion, said source region, and said drain region has a doping of a second conductivity type opposite said first conductivity type.
14. The semiconductor structure of claim 1 , further comprising a gate stack comprising a gate dielectric contacting said cap layer and a gate electrode contacting said gate dielectric, wherein said gate stack surrounds said body region of said semiconductor fin.
15. The semiconductor structure of claim 1 , wherein the first semiconductor material comprises InGaAs, and the second semiconductor material comprises InP.