Method and semiconductor device for a dedicated startup sequence in a resonant converter
A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.
1. A method of operating a semiconductor device that includes a resonant converter controller, comprising:
pulsing a lower switch drive signal initially for a preselected initial lower switch on-time;
pulsing an upper switch drive signal for a preselected initial upper switch on-time responsive to pulsing the lower switch drive signal initially;
iteratively measuring a dead time between a falling edge and a subsequent rising edge of a half bridge signal responsive to pulsing the upper switch drive signal, comparing a present dead time of a present iteration to a present startup exit value for the present iteration that is based on a present upper switch on-time for the present iteration, and, when the present dead time of the present iteration is above the startup exit value, incrementing the upper switch on-time by a preselected factor and pulsing the upper drive signal for the incremented upper switch on-time responsive to an end of the rising edge of the half bridge signal;
when the present dead time of an iteration is below the present startup exit value, pulsing the upper switch drive signal again at the present upper switch on-time and setting a lower switch on-time to the present upper switch on-time; and
commencing symmetric switching where the upper switch signal on-time and lower switching signal on-time are equal, responsive to the present dead time exceeding the startup exit value.
2. The method of claim 1 , wherein comparing the present dead time of the present iteration to the present startup exit value for the present iteration comprises comparing the present dead time to a value that is twice the present upper switch on-time.
3. The method of claim 1 , wherein incrementing the upper switch on-time by a preselected factor comprises incrementing the upper switch on-time by 50%.
4. The method of claim 1 , wherein pulsing the lower switch drive signal initially for the preselected initial lower switch on-time comprises pulsing the lower switch drive signal for lower switch on-time that is provided from a source external to the semiconductor device.
5. The method of claim 1 , further comprising, detecting a startup condition and disabling symmetric switching capability of the semiconductor device until the present dead time of an iteration is below the present startup exit value.
6. The method of claim 5 , wherein detecting the startup condition comprises detecting an input voltage exceeding a startup threshold.
7. The method of claim 1 , wherein measuring the dead time between the falling edge and the subsequent rising edge of the half bridge signal comprises measuring the time between a rising edge of a pulse produced by a negative differential detector that receives the half bridge signal and the falling edge of a pulse produced by a positive differential detector that receives the half bridge signal.
8. The method of claim 1 , further comprising, prior to pulsing the lower switch drive signal initially, activating a discharge path that is electrically between a half bridge node of the semiconductor device and an input ground for a discharge time, and disabling the discharge path at the end of the discharge time.
9. The method of claim 8 , wherein activating the discharge path comprises providing a signal to the lower switch sufficient to cause the lower switch to operate in a linear region.
10. The method of claim 8 , wherein activating the discharge path comprises activating a discharge circuit driven from a boot voltage line used to drive the upper switch.
11. A resonant power converter controller semiconductor device, comprising:
a startup sequence circuit that responds to a startup condition to disable a symmetric switching control block and pulse a lower switch drive signal for an initial time;
the startup sequence circuit further, after it pulses the lower switch drive signal for the initial time, commences a startup sequence iteration to pulse the upper switch drive signal for a present upper switch on-time, measure a dead time between an end of the pulse of the upper switch drive signal and the end of a subsequent rising edge of a half bridge signal at a half bridge node and compare the dead time to a startup exit value in a comparison circuit;
the startup sequence circuit further, when the dead time is greater than the startup exit value, increments the present upper switch on-time and conducts another startup sequence iteration using the incremented upper switch on time; and
the startup sequence circuit further, when the dead time is less than the startup exit value, pulses the upper switch drive signal for the present upper switch on-time of a most recent iteration and sets a lower switch on time to the present upper switch on-time and then enables the symmetric switching control block.
12. The semiconductor device of claim 11 , wherein the startup sequence circuit enables a discharge path between the half bridge node and a ground prior to initially pulsing the lower switch drive signal.
13. The semiconductor device of claim 12 , wherein the startup sequence circuit enables the discharge path for a preselected period of time.
14. The semiconductor device of claim 12 , wherein the startup sequence circuit enable the discharge path until a voltage of the half bridge node falls to a discharge threshold.
15. The semiconductor device of claim 12 , wherein the startup sequence circuit enables the lower switch drive signal to a linear level.
16. The semiconductor device of claim 12 , wherein the discharge path comprises:
an N-channel enable transistor that, responsive to a discharge signal at a gate of the N-channel enable transistor, drives an inverter though a pull-up source coupled to a boot voltage line used to drive the upper switch signal;
a P-channel drive transistor having a source connected to the boot voltage line and a drain connected to a drain of an N-channel drive transistor that has a source connected to the half bridge node, the P-channel drive transistor and N-channel drive transistor each having a gate coupled to an output of the inverter;
an N-channel discharge transistor having gate that is driven with the gate of the N-channel enable transistor, a drain coupled between the P-channel and drive transistor and the N-channel drive transistor, and a source coupled to ground through a discharge resistor; and
a discharge comparator coupled to the discharge resistor for sensing a half bridge voltage at the half bridge node across the discharge resistor and providing an output when the half bridge voltage falls below a discharge threshold.
17. The semiconductor device of claim 12 , wherein the discharge path comprises:
an N-channel enable transistor that, responsive to a discharge signal at a gate of the N-channel enable transistor, drives an inverter though a pull-up resistor coupled to a boot voltage line used to drive the upper switch signal;
a P-channel drive transistor having a source connected to the boot voltage line, a gate coupled to an output of the inverter, and a drain connected to a drain of an N-channel drive transistor that has a source connected to ground through a discharge resistor and a gate that is driven with the gate of the N-channel enable transistor;
a PNP discharge transistor having a base coupled to the drain of the P-channel drive transistor and to the drain of the N-channel drive transistor an emitter coupled to the half bridge node and a collector coupled to ground; and
a discharge comparator coupled to the discharge resistor for sensing a half bridge voltage at the half bridge node across the discharge resistor and providing an output when the half bridge voltage falls below a discharge threshold.
18. A resonant power converter, comprising:
an upper switch coupled between an input voltage line and a half bridge node;
a lower switch coupled between the half bridge node and an input ground;
a tank circuit including an inductance and a resonant capacitor coupled in series between the half bridge node and the input ground;
a startup sequence circuit that initially pulses the lower switch for the initial time, and then commences a startup sequence iteration to pulse the upper switch for a present upper switch on-time, measure a dead time between an end of the pulse of the upper switch and the end of a subsequent rising edge of a half bridge signal at a half bridge node and compare the dead time to a startup exit value in a comparison circuit;
when the dead time is greater than the startup exit value the startup sequence circuit increments the present upper switch on-time and conducts another startup sequence iteration using the incremented upper switch on time; and
when the dead time is less than the startup exit value the startup sequence circuit pulses the upper switch drive signal for the present upper switch on-time of a most recent iteration and sets a lower switch on time to the present upper switch on-time and then enables a symmetric switching control block.
19. The resonant power converter of claim 18 , wherein the startup sequence circuit enables a discharge path between the half bridge node and a ground prior to initially pulsing the lower switch drive signal.
20. The resonant power converter of claim 19 , wherein the startup sequence circuit enable the discharge path until a voltage of the half bridge node falls to a discharge threshold.