IP Library › Granted Patent US 9,263,468
Granted Patent B2
US 9,263,468 · App. 14/554,216 · Granted Feb 16, 2016

Display device and electronic device

Inventors: Atsushi Umezaki (Kanagawa, JP); Hiroyuki Miyake (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1214G02F1/1368G02F1/136286H01L27/12H01L27/124G09G3/20G09G3/2022G09G3/3233G09G3/3275G09G3/342G09G3/3426G09G3/3685G09G2300/043G09G2300/0852G09G2310/027G09G2310/0248G09G2310/0262G09G2310/0275G09G2310/0297G09G2320/0233G09G2330/021G09G2340/02G09G2352/00H01L27/156H01L29/42384H01L2924/0002
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Quick Facts
Patent No.
US 9,263,468
App. No.
14/554,216
Granted
Feb 16, 2016
Kind
B2
Abstract

An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

Claims (54)

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, and a seventh wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the first transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the sixth wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the seventh wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the fifth wiring, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to the first wiring through at least a first conductive layer,

wherein one of a source and a drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring through at least a second conductive layer,

wherein one of a source and a drain of the eighth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,

wherein the first conductive layer and the second conductive layer have a transparency, and

wherein the first conductive layer has a first width and the second conductive layer has a second width narrower than the first width.

2. The semiconductor device according to claim 1 , wherein a value of a ratio W/L of a channel width W to a channel length L of the seventh transistor is 1/40 to 1/10 than that of the first transistor.

3. The semiconductor device according to claim 1 , wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.

4. A display device comprising a pixel and the semiconductor device according to claim 1 , wherein the pixel is electrically connected to the third wiring.

5. A display module comprising a Flexible Printed Circuit (FPC) and a display device according to claim 1 .

6. An electronic device comprising the display module according to claim 1 , wherein the electronic device is one selected from the group consisting of a camera, a computer, an image reproducing device, a goggle-type display, and a game machine.

7. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, and a seventh wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the fourth wiring through at least a first conductive layer, and the other of the source and the drain of the first transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the sixth wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the seventh wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the fifth wiring, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring through at least a second conductive layer,

wherein one of a source and a drain of the eighth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,

wherein the first conductive layer and the second conductive layer have a transparency, and

wherein the first conductive layer has a first width and the second conductive layer has a second width narrower than the first width.

8. The semiconductor device according to claim 7 , wherein a value of a ratio W/L of a channel width W to a channel length L of the seventh transistor is 1/40 to 1/10 than that of the first transistor.

9. The semiconductor device according to claim 7 , wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.

10. A display device comprising a pixel and the semiconductor device according to claim 7 , wherein the pixel is electrically connected to the third wiring.

11. A display module comprising a Flexible Printed Circuit (FPC) and a display device according to claim 7 .

12. An electronic device comprising the display module according to claim 7 , wherein the electronic device is one selected from the group consisting of a camera, a computer, an image reproducing device, a goggle-type display, and a game machine.

13. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, and a seventh wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the first transistor is electrically connected to the third wiring through at least a first conductive layer,

wherein one of a source and a drain of the second transistor is electrically connected to the sixth wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the seventh wiring, the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the fifth wiring, the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring, the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring through at least a second conductive layer,

wherein one of a source and a drain of the eighth transistor is electrically connected to the sixth wiring, the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,

wherein the first conductive layer and the second conductive layer have a transparency, and

wherein the first conductive layer has a first width and the second conductive layer has a second width narrower than the first width.

14. The semiconductor device according to claim 13 , wherein a value of a ratio W/L of a channel width W to a channel length L of the seventh transistor is 1/40 to 1/10 than that of the first transistor.

15. The semiconductor device according to claim 13 , wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.

16. A display device comprising a pixel and the semiconductor device according to claim 13 , wherein the pixel is electrically connected to the third wiring.

17. A display module comprising a Flexible Printed Circuit (FPC) and a display device according to claim 13 .

18. An electronic device comprising the display module according to claim 13 , wherein the electronic device is one selected from the group consisting of a camera, a computer, an image reproducing device, a goggle-type display, and a game machine.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2015
From: UMEZAKI, ATSUSHI; MIYAKE, HIROYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 034828/0184 →
Priority Claims (1)
JP 2006-269905 · Sep 29, 2006 · national
Continuity (4)
Continuation 13974328 · Aug 23, 2013
Continuation 13174895 · Jul 1, 2011
Continuation 11853215 · Sep 11, 2007
Related Publication 20150077676A1 · Mar 19, 2015