Mask-aware routing and resulting device

1. A method comprising:

laying-out continuous metal lines in a semiconductor design layout;

routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules;

determining locations of the cut or block masks to generate signal lines from the continuous metal lines to connect cells within the semiconductor design layout;

checking whether the placement of the cut or block masks satisfies the cut or block mask design rules;

determining that two candidate cut or block mask polygons for routing the metal routing layer would violate the cut or block mask design rules; and

combining the two candidate cut or block mask polygons into a single cut or block mask polygon to satisfy the cut or block mask design rules.

2. The method according to claim 1 , wherein portions of the continuous metal lines used in the metal routing layer form the signal lines, and remaining portions of the continuous metal lines form dummy lines.

3. The method according to claim 2 , further comprising:

accounting for timing delays resulting from the signal lines during the routing.

4. The method according to claim 2 , further comprising:

accounting for timing delays resulting from the dummy lines during the routing to generate a dummy-line-aware timing closure.

5. The method according to claim 1 , wherein the cut or block mask design rules are based on proximity of the two candidate cut or block mask polygons.

6. The method according to claim 1 , wherein the masks are block masks.

7. The method according to claim 1 , wherein the masks are cut masks.

8. An apparatus comprising:

a processor; and

a memory including computer program code for one or more programs, the memory and the computer program code configured to, with the processor, cause the apparatus to perform the following:

layout continuous metal lines in a semiconductor design layout;

route a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules;

determine locations of cut or block masks to generate the signal lines from the continuous metal lines to connect cells within the semiconductor design layout;

check whether the placement of the cut or block masks satisfies the cut or block mask design rules

determine that two candidate cut or block mask polygons for routing the metal routing layer would violate the cut or block mask design rules; and

combine the two candidate cut or block mask polygons into a single cut or block mask polygon to satisfy the cut or block mask design rules.

9. The apparatus according to claim 8 , wherein portions of the continuous metal lines used in the metal routing layer form the signal lines, and remaining portions of the continuous metal lines form dummy lines.

10. The apparatus according to claim 9 , wherein the apparatus is further caused to:

account for timing delays resulting from the signal lines during the routing.

11. The apparatus according to claim 9 , wherein the apparatus is further caused to:

account for timing delays resulting from the dummy lines during the routing to generate a dummy-line-aware timing closure.

12. The apparatus according to claim 8 , wherein the cut or block mask design rules are based on proximity of the two candidate cut or block mask polygons.

13. The apparatus according to claim 8 , wherein the masks are block masks.

14. The apparatus according to claim 8 , wherein the masks are cut masks.

15. A method comprising:

forming continuous metal lines above a substrate of a semiconductor device;

determining, by a processor, locations of cut or block masks based on cut or block mask design rules for designing a metal routing layer out of the continuous metal lines;

removing portions of the continuous metal lines based on the cut or block masks forming the metal routing layer;

determining locations of the cut or block masks to generate signal lines from the continuous metal lines to connect cells within the semiconductor design layout;

checking whether the placement of the cut or block masks satisfies the cut or block mask design rules;

determining that two candidate cut or block mask polygons in designing the metal routing layer would violate a cut or block mask design rule; and

forming a single cut or block mask polygon by combining the two candidate cut or block mask polygons to satisfy the cut or block mask design rule.