Composite views for IP blocks in ASIC designs
A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.
1. A method comprising:
obtaining constraints for a plurality of application specific integrated circuits (ASIC) designs in which a particular IP core is used;
determining, by a computing device, composite constraints for the particular IP core based on the constraints for the plurality of ASIC designs, the composite constraints being within all constraints for the plurality of ASIC designs; and
identifying, by the computing device, a freedom of change to update the particular IP core based on the composite constraints.
2. The method of claim 1 , further comprising obtaining information identifying the ASIC designs in which the particular IP core is used, the information being used to obtain the constraints.
3. The method of claim 1 , wherein updates to the particular IP core within the composite constraints minimize impact to the plurality of ASIC designs.
4. The method of claim 1 , wherein the composite constraints include at least one of: a layout composite constraint, a timing composite constraint, a power composite constraint, and a noise composite constraint.
5. The method of claim 4 , further comprising identifying all circuit layout blockages associated with the plurality of ASIC designs, the circuit layout blockages corresponding to the layout composite constraint.
6. The method of claim 4 , wherein the timing composite constraint identifies a maximum timing slack value that is within all timing constraints associated with the plurality of ASIC designs.
7. The method of claim 4 , wherein the power composite constraint identifies a maximum power value that is within all power constraints associated with the plurality of ASIC designs.
8. The method of claim 4 , wherein the noise composite constraint identifies a maximum noise value that is within all noise constraints associated with the plurality of ASIC designs.
9. The method of claim 1 , further comprising updating a file associated with the particular IP core based on information regarding the composite constraints.
10. The method of claim 9 , wherein the file includes at least one of: a timing library, a power library, a noise abstract file, and a physical information file.
11. The method claim 9 , further comprising performing at least one of: a timing closure process, a power analysis, a noise analysis, and place and routing analysis using the file.
12. A computer program product for generating a composite view for an intellectual property (IP) core, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computing device to cause the computing device to perform a method comprising:
obtaining constraints for a plurality of application specific integrated circuits (ASIC) designs in which the IP core is used;
determining composite constraints for the IP core based on the constraints for the plurality of ASIC designs, the composite constraints being within all of the constraints for the plurality of ASIC designs; and
generating the composite view for the IP core visually displaying the composite constraints.
13. The computer program product of claim 12 , wherein the composite view identifies a freedom of change to update the particular IP core.
14. The computer program product of claim 12 , wherein the composite view includes at least one of: a layout composite view, a timing composite view, a power composite view, and a noise composite view.
15. The computer program product of claim 14 , wherein the layout composite view illustrates all circuit layout blockages associated with the plurality of ASIC designs.
16. The computer program product of claim 14 , wherein the timing composite view illustrates a maximum timing slack value that is within all timing constraints associated with the plurality of ASIC designs.
17. The computer program product of claim 14 , wherein the power composite view illustrates a maximum power value that is within all power constraints associated with the plurality of ASIC designs.
18. The computer program product of claim 14 , wherein the noise composite view illustrates a maximum noise value that is within all noise constraints associated with the plurality of ASIC designs.
19. A computer program product for generating composite views for an intellectual property (IP) core, said computer program product comprising:
a non-transitory computer readable storage medium:
first program instructions executable by a computing device to cause the computing device to obtain constraints for a plurality of application specific integrated circuits (ASIC) designs in which the IP core is used; and
second program instructions executable by the computing device to cause the computing device to determine composite constraints for the IP core based on the constraints for the plurality of ASIC designs, the composite constraints being within all of the constraints for the plurality of ASIC designs.
20. The computer program product of claim 19 , wherein the file includes at least one of: a timing library, a power library, a noise abstract file, and a physical information file.