Multilevel inverters and their components

1. A multilevel inverter comprising:

a first half bridge connected in series with a second half bridge, the first and second half bridges each comprising a semiconductor-based switch having a channel, the semiconductor-based switch being configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation, wherein during the third mode of operation a gate of the semiconductor-based switch is biased relative to a source of the semiconductor-based switch at a voltage that is less than a threshold voltage of the semiconductor-based switch;

a third half bridge having a low-side switch coupled to a high-side switch; and

a first filter and a second filter,

wherein the first filter is coupled between an output node of the first half bridge and a power terminal of the high-side switch, the first filter being directly connected to ground, and

wherein the second filter is coupled between an output node of the second half bridge and a power terminal of the low-side switch, the second filter being directly connected to ground,

such that the low-side switch and the high-side switch of the third half bridge are to be switched at a substantially lower frequency than a switching frequency of the semiconductor-based switch.

2. The multilevel inverter of claim 1 , wherein the semiconductor-based switch comprises a III-Nitride transistor.

3. The multilevel inverter of claim 1 , wherein the semiconductor-based switch comprises an enhancement-mode transistor coupled to a III-Nitride depletion-mode transistor.

4. A multilevel inverter, comprising:

a first half bridge connected in series with a second half bridge, the first and second half bridges each comprising a plurality of switches;

a third half bridge comprising a high-side switch coupled to a low-side switch at an output node of the third half bridge, the high-side switch including a first gate, a first power terminal and a second power terminal, the low-side switch including a second gate, a third power terminal and a fourth power terminal, wherein the second power terminal of the high-side switch and the third power terminal of the low-side switch are coupled to the output node of the third half bridge; and

a first low-pass filter and a second low-pass filter;

wherein the first low-pass filter is coupled between an output node of the first half bridge and the first power terminal of the high-side switch, the first low-pass filter being directly connected to ground, and

wherein the second low-pass filter is coupled between an output node of the second half bridge and the fourth power terminal of the low-side switch, the second low-pass filter being directly connected to the ground.

5. The multilevel inverter of claim 4 , wherein the plurality of switches of the first and second half bridges are configured to be switched at a frequency of at least 50 kHz, and the high-side switch and the low-side switch are configured to be switched at a frequency of 1 kHz or less.

6. The multilevel inverter of claim 4 , wherein the first low-pass filter and the second low-pass filter each include an inductor and a capacitor.

7. The multilevel inverter of claim 4 , wherein the plurality of switches of the first and second half bridges are configured to be switched at a frequency that is at least five times greater than a switching frequency of the high-side switch and the low-side switch.

8. The multilevel inverter of claim 4 , wherein at least one of the plurality of switches comprises a III-Nitride transistor.

9. The multilevel inverter of claim 4 , wherein at least one of the plurality of switches comprises an enhancement-mode transistor coupled to a III-Nitride depletion-mode transistor.