Methods of forming reduced resistance local interconnect structures and the resulting devices

1. A method, comprising:

forming a layer of insulating material above first and second transistors that are formed above first and second spaced-apart active regions, respectively;

within said layer of insulating material:

forming a set of initial device-level contacts for each of said first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact; and

forming an initial local interconnect structure that is conductively coupled to one of said initial device-level contacts of said first transistor and conductively coupled to one of said initial device-level contacts of said second transistor;

performing at least one recess etching process so as to remove said initial local interconnect structure and portions, but not all, of said initial device-level contacts for each of said first and second transistors so as to thereby define a local interconnect recess in said layer of insulating material and a plurality of recessed device-level contacts for each of said first and second transistors; and

forming:

a copper local interconnect structure in said local interconnect recess that is conductively coupled to one of said recessed device-level contacts of said first transistor and conductively coupled to one of said recessed device-level contacts of said second transistor; and

a copper cap above each of said recessed device-level contacts of said first and second transistors that are not conductively coupled to said copper local interconnect structure.

2. The method of claim 1 , wherein an upper surface of said copper local interconnect structure and an upper surface of each of said copper caps is substantially planar with an upper surface of said layer of insulating material.

3. The method of claim 1 , wherein said initial device-level contacts of each of said first and second transistors and said initial local interconnect structure is comprised of the same first material.

4. The method of claim 3 , wherein said first material is tungsten.

5. The method of claim 1 , wherein said initial device-level contacts for each of said first and second transistors and said initial local interconnect structure are formed by:

performing at least one common deposition process operation to deposit a first material into openings formed in said layer of insulating material; and

performing at least one common CMP process to remove portions of said first material positioned outside of said openings and above an upper surface of said layer of insulating material.

6. The method of claim 1 , wherein said source/drain contacts are line-type structures and said gate contact is a post-type structure.

7. The method of claim 1 , wherein said source/drain contacts comprise a trench silicide structure.

8. The method of claim 1 , wherein said copper local interconnect structure is formed such that it has a first self-aligned contact interface with said recessed device-level contact of said first transistor and a second self-aligned contact interface with said recessed device-level contact of said second transistor.

9. The method of claim 8 , wherein each of said copper caps is formed such that it has a self-aligned contact interface with said recessed device-level contact to which said copper cap is conductively coupled.

10. A method, comprising:

forming a layer of insulating material above first and second transistors that are formed above first and second spaced-apart active regions, respectively;

within said layer of insulating material:

forming a set of initial device-level contacts for each of said first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact; and

forming an initial local interconnect structure that is conductively coupled to one of said initial device-level contacts of said first transistor and conductively coupled to one of said initial device-level contacts of said second transistor, wherein said initial device-level contacts of each of said first and second transistors and said initial local interconnect structure are comprised of the same first material;

performing at least one recess etching process so as to remove said initial local interconnect structure and portions, but not all, of said initial device-level contacts for each of said first and second transistors so as to thereby define a local interconnect recess in said layer of insulating material and a plurality of recessed device-level contacts for each of said first and second transistors; and

forming:

a copper local interconnect structure in said local interconnect recess that is conductively coupled to one of said recessed device-level contacts of said first transistor and conductively coupled to one of said recessed device-level contacts of said second transistor; and

a copper cap above each of said recessed device-level contacts of said first and second transistors that are not conductively coupled to said copper local interconnect structure, wherein an upper surface of said copper local interconnect structure and an upper surface of each of said copper caps is substantially planar with an upper surface of said layer of insulating material.

11. The method of claim 10 , wherein said first material is tungsten.

12. The method of claim 10 , wherein said initial device-level contacts for each of said first and second transistors and said initial local interconnect structure are formed by:

performing at least one common deposition process operation to deposit a first material into openings formed in said layer of insulating material; and

performing at least one common CMP process to remove portions of said first material positioned outside of said openings and above an upper surface of said layer of insulating material.

13. The method of claim 10 , wherein said source/drain contacts are line-type structures and said gate contact is a post-type structure.

14. The method of claim 10 , wherein said source/drain contacts comprise a trench silicide structure.

15. A method, comprising:

forming a layer of insulating material above first and second transistors that are formed above first and second spaced-apart active regions, respectively;

within said layer of insulating material:

forming a set of initial device-level contacts for each of said first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact; and

forming an initial local interconnect structure that is conductively coupled to one of said initial device-level contacts of said first transistor and conductively coupled to one of said initial device-level contacts of said second transistor;

performing at least one recess etching process so as to remove said initial local interconnect structure and portions, but not all, of said initial device-level contacts for each of said first and second transistors so as to thereby define a local interconnect recess in said layer of insulating material and a plurality of recessed device-level contacts for each of said first and second transistors; and

forming a layer of copper so as to over-fill said local interconnect recess and an opening in said layer of insulating material above each of said recessed device-level contacts, wherein said layer of copper has a substantially planar upper surface that is positioned above an upper surface of said layer of insulating material and wherein formation of said layer of copper results in the formation of:

a copper local interconnect structure in said local interconnect recess that is conductively coupled to one of said recessed device-level contacts of said first transistor and conductively coupled to one of said recessed device-level contacts of said second transistor; and

a copper cap above each of said recessed device-level contacts of said first and second transistors that are not conductively coupled to said copper local interconnect structure;

forming a patterned etch mask above the upper surface of said layer of copper; and

performing an etching process through said patterned etch mask to remove portions of said layer of copper positioned above said upper surface of said layer of insulating material so as to thereby define a copper line that is formed integral with said copper local interconnect structure and a copper via that is formed integral with at least one of said copper caps, wherein said copper line and said copper via are positioned above said upper surface of said layer of insulating material.

16. The method of claim 15 , wherein said initial device-level contacts of each of said first and second transistors and said initial local interconnect structure is comprised of the same first material.

17. The method of claim 16 , wherein said first material is tungsten.