Topological method to build self-aligned MTJ without a mask

1. A device comprising:

a low-k dielectric layer;

a metal layer recessed in the low-k dielectric layer;

a first electrode formed on the metal layer;

a self-aligned magnetic tunnel junction (MTJ) formed on the first electrode;

a second electrode formed on the MTJ;

a silicon nitride-based layer formed on the low-k dielectric layer and adjacent to an outer edge of the first electrode, the MTJ, and the second electrode; and

a second metal layer within a trench and a via etched into an ultra-low-k (ULK) dielectric layer, the ULK layer located over the silicon nitride-based layer and the second electrode.

2. The device according to claim 1 , wherein the metal layer is recessed 5 nanometer (nm) to 50 nm in the low-k dielectric layer.

3. The device according to claim 1 , wherein the self-aligned MTJ is formed to a width of 20 nm to 50 nm.

4. The device according to claim 1 , wherein the first and second electrode are formed of tantalum (Ta).

5. A device comprising:

a first electrode over a first metal layer, the first metal layer recessed in a low-k dielectric layer;

a magnetic tunnel junction (MTJ) layer over the first electrode;

a second electrode over the MTJ layer, wherein portions of the second electrode, the MTJ layer, and the first electrode have been removed down to the low-k dielectric layer;

a silicon nitride-based layer over the second electrode and the low-k dielectric layer;

patterning stacks on the silicon nitride-based layer and the second electrode, the patterning stacks being laterally separated;

trenches configured in place of the patterning stacks; and

a second metal layer above the first metal layer and the MTJ layer and in the trenches.

6. The device according to claim 5 , wherein the first metal layer is recessed in the low-k dielectric layer by wet etching to a depth of 5 nanometer (nm) to 50 nm.

7. The device according to claim 5 , wherein the first and second electrodes and the MTJ layer are formed by directional deposition with minimal sidewall coverage.

8. The device according to claim 5 , the portions of the second electrode, the MTJ layer, and the first electrode have been removed by:

forming a second silicon nitride-based layer over the second electrode;

planarizing the other silicon nitride-based layer down to the second electrode, a remaining portion of the other silicon nitride-based layer located above the first metal layer; and

etching the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer on each side of the remaining portion of the other silicon nitride-based layer.

9. The device according to claim 5 , wherein the patterning stacks are formed by:

planarizing the silicon nitride-based layer down to the second electrode;

forming an ultra-low-k (ULK) dielectric layer over the planarized silicon nitride-based layer and the second electrode;

forming a hard mask layer over the ULK layer;

forming an organic planarization layer (OPL) over the ULK layer;

forming a silicon-containing anti-reflective coating (SiARC) layer over the OPL layer;

forming photoresist features corresponding to the patterning stacks on the SiARC layer, the photoresist features being laterally separated from each other;

etching the SiARC, OPL, hard mask, and ULK layers down to the second electrode and silicon nitride-based layer using the photoresist features; and

removing the photoresist features, the SiARC and OPL layers.

10. The device according to claim 5 , wherein the second electrode and the MTJ layer are etched between the patterning stacks down to the first electrode.

11. The device according to claim 9 , wherein the trenches are formed by:

forming a passivation layer over the patterning stacks, the silicon nitride-based layer, and the first electrode;

forming an oxide layer over the passivation layer;

planarizing the oxide layer down to the hard mask layer;

recessing the oxide and passivation layers;

forming a second hard mask layer over the oxide and passivation layers and in each recess;

planarizing the other hard mask layer down to the hard mask layer; and

etching the hard mask, the second hard mask layer, the ULK, and the passivation layers down to the second electrode.

12. The device according to claim 5 , wherein the second metal layer is formed by:

dual-damascene patterning.

13. A device comprising:

a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer;

a magnetic tunnel junction (MTJ) layer over the first electrode;

a second electrode over the MTJ layer, wherein portions of the second electrode, the MTJ layer, and the first electrode have been removed down to the low-k dielectric layer; and

a silicon nitride-based layer over the second electrode and the low-k dielectric layer, wherein the silicon nitride-based layer has been planarized down to the second electrode, and

wherein the portions of the second electrode, the MTJ layer, and the first electrode are removed by:

forming a second silicon nitride-based layer over the second electrode;

planarizing the other silicon nitride-based layer down to the second electrode, a remaining portion of the other silicon nitride-based layer located above the metal layer, and

etching the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer on each side of the remaining portion of the other silicon nitride-based layer.

14. The device according to claim 13 , wherein the metal layer is recessed in the low-k dielectric layer by wet etching to a depth of 5 nanometer (nm) to 50 nm.

15. The device according to claim 13 , wherein the first and second electrodes and the MTJ layer have been formed by directional deposition with minimal sidewall coverage.

16. The device according to claim 13 , further comprising a second metal layer, the second metal layer formed by dual-damascene patterning, with a trench above the second electrode for electrical contact.

17. The device according to claim 16 , wherein the second metal layer is formed by:

forming an ultra-low-k (ULK) dielectric layer over the planarized silicon nitride-based layer and the second electrode;

etching a trench and a via in the ULK layer; and

forming the second metal layer in the trench and the via.