Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap

1. A method of forming an integrated circuit device, the method comprising:

forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element;

forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and directly contacting a top surface of the first UBM layer;

etching the first UBM layer to remove a portion of the first UBM layer, wherein etching first UBM layer comprises removing the protection layer from an upper portion of the sidewalls of the conductive element; and

forming a cap layer over a top surface of the conductive element.

2. The method of claim 1 , wherein forming the conductive element comprises:

forming a mask layer over the UBM layer;

patterning the mask layer to form an opening in the mask layer; and

forming the conductive element in the opening.

3. The method of claim 1 , wherein the conductive element is formed by sputtering, printing, electro plating, electroless plating, electro-chemical plating or chemical vapor deposition.

4. The method of claim 1 , wherein etching the second UBM layer comprises a wet etching process.

5. The method of claim 1 , wherein forming the protection layer comprises forming the protection layer having a thickness ranging from about 500 angstroms to about 10,000 angstroms.

6. The method of claim 1 , wherein forming the protection layer comprises forming the protection layer comprising at least one layer of a dielectric material.

7. The method of claim 1 , further comprising etching the protection layer to expose the portion of the first UBM layer.

8. The method of claim 7 , wherein etching the protection layer comprises removing the protection layer from the top surface of the conductive element.

9. The method of claim 1 , wherein the first UBM layer is etched using a dry etching process.

10. The method of claim 1 , wherein forming the cap layer comprises forming the cap layer over the upper portion of the sidewalls of the conductive element.

11. The method of claim 1 , wherein removing the protection layer from the upper portion of the sidewalls comprises exposing the upper portion of the sidewalls of the conductive having a length ranging from about 2 microns (μm) to about 8 μm.

12. The method of claim 1 , further comprising bonding the conductive element to a second substrate.

13. The method of claim 12 , wherein bonding the conductive element to the second substrate comprises reflowing a solder layer between the conductive element and the second substrate, and the cap layer is between the conductive element and the solder layer.

14. A method of forming an integrated circuit device, the method comprising:

plating a conductive element over a first substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

depositing a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer, wherein the protection layer exposes an upper portion of the sidewalls of the conductive element;

forming a cap layer over a top surface and the upper portion of the sidewalls of the conductive element; and

bonding the conductive element to a second substrate using a solder layer, wherein the cap layer is between the conductive element and the solder layer.

15. The method of claim 14 , wherein bonding the conductive element to the second substrate comprises bonding the conductive element to a contact pad or a conductive trace.

16. The method of claim 14 , wherein plating the conductive element comprises plating a copper-containing material.

17. The method of claim 14 , further comprising etching the first UBM layer using the protection layer over the sidewalls of the conductive element as a mask.

18. The method of claim 14 , wherein plating the conductive element comprises:

forming a mask layer over a top surface of the second UBM layer;

patterning the mask layer to form an opening; and

plating the conductive element in the opening.

19. A method of forming an integrated circuit device, the method comprising:

plating a conductive element over a first substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer;

depositing a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer;

etching the first UBM layer using the protection layer as a mask, wherein etching the first UBM layer comprises removing the protection layer from an upper portion of the sidewalls of the conductive element;

forming a multi-layered cap layer over a top surface and the upper portion of the sidewalls of the conductive element; and

bonding the conductive element to a second substrate using a solder layer, wherein the cap layer is between the conductive element and the solder layer.

20. The method of claim 19 , wherein bonding the conductive element to the second substrate comprises bonding the conductive element to a contact pad or a conductive trace.