High-reliability, low-resistance contacts for nanoscale transistors
Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.
1. An apparatus, comprising:
a tapered vertical column containing a conducting material, the tapered vertical column including a top surface having a top surface width, and sidewalls that slope inward from the top surface; and
an enlarged pedestal formed in a valley at a lower end of the tapered vertical column, the pedestal at least partially filled with the conducting material, the conducting material underlying and in direct contact with at least a portion of an epitaxial semiconductor region, the pedestal having a pedestal width that is wider than the top surface width, and the epitaxial semiconductor region including one or more of doped silicon or silicon germanium.
2. An apparatus, comprising:
a tapered vertical column containing a conducting material, the tapered vertical column including a top surface having a top surface width, and sidewalls that slope inward from the top surface;
an enlarged pedestal formed in a valley at a lower end of the tapered vertical column, the pedestal at least partially filled with the conducting material abutting and in direct contact with a region of epitaxial semiconductor material, the pedestal having a pedestal width that is wider than the top surface width, the epitaxial semiconductor material including one or more of doped silicon or silicon germanium;
a substrate and a plurality of fins that extend from the substrate into the valley;
a gate electrode overlying the fins in a transverse orientation; and
a gate contact coupled to a top surface of the gate electrode.
3. The apparatus of claim 2 wherein the fins include epitaxial extensions that increase a fin contact surface area.
4. The apparatus of claim 2 , further comprising a silicide layer in contact with one or more surfaces of the fins.
5. The apparatus of claim 2 wherein the fins are arranged substantially parallel to one another.
6. The apparatus of claim 1 wherein the pedestal is located adjacent to raised isolation regions containing an insulating material.
7. The apparatus of claim 1 wherein the conducting material includes one or more of tungsten, copper, silver, aluminum, titanium, titanium nitride, or combinations thereof.
8. The apparatus of claim 2 wherein
each fin includes a source region, a drain region, and a channel region coupling the source and drain regions, and
the gate electrode covers the channel regions of the fins.
9. The apparatus of claim 3 wherein the epitaxial extensions have diamond-shaped profiles.
10. An apparatus, comprising:
a silicon substrate;
isolation regions in the silicon substrate, the isolation regions having raised portions;
an array of semiconducting fins between the raised portions, the fins being substantially parallel to one another and extending above the silicon substrate;
a gate electrode overlying the array of semiconducting fins; and
tapered contacts to the fins, the tapered contacts having
a top surface having a top contact width,
a bottom surface, and
sidewalls that slope inward from the top surface to the bottom surface.
11. The apparatus of claim 10 , further comprising epitaxial extensions from the semiconducting fins.
12. The method of claim 11 wherein the epitaxial extensions are spaced apart from one another.
13. The method of claim 11 wherein the epitaxial extensions increase a fin contact area by at least a factor of 10.
14. The apparatus of claim 10 , further comprising a protective liner covering the fins.
15. The method of claim 14 wherein the protective liner is made of silicon nitride.
16. The apparatus of claim 10 , further comprising an encapsulant covering the fins.
17. The apparatus of claim 16 wherein the encapsulant is made of amorphous silicon.
18. The apparatus of claim 10 , further comprising an insulating layer above the fins.
19. The apparatus of claim 10 wherein the tapered contacts include a bottom pedestal having a pedestal width that exceeds the top contact width.
20. A device comprising:
a semiconductor substrate;
a fin including a source region, a drain region, and a channel extending between the source and drain regions;
a gate overlying the fin in a transverse orientation to the fin; and
contacts to the source region, the drain region, and the gate, at least one of the contacts including:
a tapered vertical column containing a conducting material, the tapered vertical column including a top surface having a top surface width, and sidewalls that slope inward from the top surface; and
an enlarged pedestal formed in a valley at a lower end of the tapered vertical column, the pedestal at least partially filled with the conducting material abutting and in direct contact with a region of epitaxial semiconductor material, the pedestal having a pedestal width that is wider than the top surface width.
21. The apparatus of claim 1 wherein the pedestal includes at least one void region that is not filled with the conducting material.
22. The device of claim 20 wherein the pedestal includes at least one void region that is not filled with the conducting material.