Semiconductor devices with field plates
A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
1. A III-N device, comprising:
a III-N material layer;
a first insulator layer on a surface of the III-N material layer, the first insulator layer having a first recess formed therein;
a first electrode in the first recess;
a stack on an opposite side of the first insulator layer from the III-N material layer, wherein the stack comprises a second insulator layer, an etch stop layer and an electrode defining layer; and
a second electrode, wherein a second recess is formed in the electrode defining layer and in the etch stop layer, and the second electrode is in the second recess.
2. The device of claim 1 , wherein a portion of the first electrode is over a top surface of the first insulating layer.
3. The device of claim 2 , wherein a portion of the second electrode is over a top surface of the electrode defining layer.
4. The device of claim 2 , wherein the first recess further extends into the III-N material layer.
5. The device of claim 4 , wherein a first portion of the III-N material layer has a first composition and a second portion of the III-N material layer has a second composition, wherein a difference between the first composition and the second composition causes a 2DEG channel to be formed in the III-N material layer.
6. The device of claim 5 , wherein the first insulator layer is less than 100 nanometers.
7. The device of claim 1 , wherein the recess extends all the way through a first portion of the III-N material layer and into a second portion of the III-N material layer.
8. The device of claim 1 , wherein the first electrode includes a field plate.
9. The device of claim 1 , wherein the first electrode comprises a gate, and the device further comprises a source and a drain.
10. The device of claim 9 , wherein a positive voltage must be applied to the gate to induce a 2DEG in the gate region of the III-N material layer.
11. The device of claim 10 , wherein the device is an enhancement-mode device.
12. The device of claim 1 , wherein the first insulator layer is formed of an oxide or nitride.
13. The device of claim 1 , wherein the second insulator layer and the electrode defining layer is formed of an oxide or nitride.
14. The device of claim 1 , wherein the second insulator layer is at least 100 nanometers thick.
15. The device of claim 1 , wherein the first insulator layer and the second insulator layer are formed of different materials.
16. A III-N device, comprising:
a III-N material layer;
an insulator layer on a surface of the III-N material layer;
a first electrode defining layer on an opposite side of the insulator layer from the III-N material layer;
a first electrode, wherein a first recess is formed through the first electrode defining layer, through the insulator layer and part way through the III-N material layer and the first electrode is in the first recess;
a stack on an opposite side of the first electrode defining layer from the insulator layer, wherein the stack comprises an etch stop layer and a second electrode defining layer; and
a second electrode, wherein a second recess is formed in the second electrode defining layer and in the etch stop layer, and the second electrode is in the second recess.
17. The device of claim 16 , wherein a first portion of the III-N material layer has a first composition and a second portion of the III-N material layer has a second composition, wherein a difference between the first composition and the second composition causes a 2DEG channel to be formed in the III-N material layer.
18. The device of claim 16 , wherein the insulator layer is less than 100 nanometers.
19. The device of claim 17 , wherein the recess extends all the way through the first portion of the III-N material layer and into the second portion of the III-N material layer.
20. The device of claim 16 , further comprising a second insulator layer between the first electrode defining layer and the etch stop layer.
21. The device of claim 16 , wherein the second electrode is electrically connected to the first electrode.
22. The device of claim 16 , wherein the first electrode comprises a gate, and the device further comprises a source and a drain.
23. The device of claim 22 , wherein a positive voltage must be applied to the gate to induce a 2DEG in the gate region of the III-N material layer.
24. The device of claim 23 , wherein the device is an enhancement-mode device.
25. The device of claim 16 , wherein either the first electrode or the second electrode or both includes a field plate.
26. The device of claim 25 , wherein the field plate is a slant field plate.
27. The device of claim 26 , wherein the first electrode defining layer and the insulator layer are formed of different materials.
28. The device of claim 27 , wherein the electrode defining layers comprise SiN.