IP Library › Granted Patent US 9,847,300
Granted Patent B2
US 9,847,300 · App. 15/144,917 · Granted Dec 19, 2017

Method of manufacturing semiconductor device

Inventors: Nobutaka Sakai (Kameda-gun, JP); Mamoru Otake (Kameda-gun, JP); Koji Saito (Kameda-gun, JP); Tomishi Takahashi (Kameda-gun, JP)
Assignee: Renesas Electronics Corporation
H01L23/544H01L21/4825H01L21/561H01L21/6836H01L21/78H01L22/10H01L22/20H01L24/97H01L2221/68327H01L2223/54406H01L2223/54413H01L2223/54426H01L2223/54433H01L2223/54486H01L2223/54493H01L2224/05554H01L2224/32245H01L2224/45144H01L2224/48091H01L2224/48247H01L2224/49171H01L2224/83192H01L2224/859H01L2224/92247H01L2924/12042H01L2924/181
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Quick Facts
Patent No.
US 9,847,300
App. No.
15/144,917
Granted
Dec 19, 2017
Kind
B2
Abstract

Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

Claims (18)

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) providing a plurality of substrates each including a plurality of chip mounting portions and external terminal forming portions;

(b) in each of the substrates, mounting a semiconductor chip on each of the chip mounting portions;

(c) after the step (b), in each of the substrates, electrically coupling a bonding pad of the semiconductor chip and the external terminal forming portion with a conductive component;

(d) after the step (c), in each of the substrates, sealing the semiconductor chip and the conductive component with a resin sealing body;

(e) after the step (d), in each of the substrates, forming a mark including product information on a surface of the resin sealing body;

(f) after the step (e), in each of the substrates, forming a plated layer on a surface of the external terminal forming portion exposed to an outside of the resin sealing body;

(g) after the step (f), in each of the substrates, singulating the substrate into a plurality of semiconductor devices by cutting the resin sealing body and the external terminal forming portion;

(h) after the step (g), in each of the semiconductor devices, carrying out a testing for screening a characteristic defect of the semiconductor chip sealed with the resin sealing body;

(i) after the step (h), in each of the semiconductor devices, carrying out a visual inspection for screening a visual defect; and

(j) among the semiconductor devices, shipping the semiconductor device determined to be nondefective in the step (i),

wherein unique identification information is attached to each of the substrate, the chip mounting portion of the substrate, the semiconductor chip, and a rack for storing and transporting the substrate,

wherein in each of the step (b) and the subsequent steps, a manufacturing history of each of the steps and the identification information are associated with each other via a server, thereby process control of the semiconductor devices is performed, and

wherein the process control is performed in a unit of rack up to the step (c), while on and after the step (d), the process control is performed in a unit of lot.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the identification information attached to the semiconductor chip includes a semiconductor wafer number, a diffusion lot number, positional information regarding the semiconductor chip in a semiconductor wafer, and nondefective product/defective product information regarding the semiconductor chip that are wafer process information regarding the semiconductor chip.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein a same diffusion lot number is attached to a plurality of the semiconductor chips manufactured in a same diffusion process, the diffusion lot number and identification information of the rack are associated with each other, and thereby process control of the semiconductor devices is performed.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein each piece of the identification information is formed in a form of a two-dimensional code.

5. The method of manufacturing a semiconductor device according to claim 4 , wherein the two-dimensional codes are marked by a laser beam, respectively.

Assignments (1)
ADDRESS CHANGE Recorded Jun 19, 2018
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 046390/0398 →
Priority Claims (1)
JP 2012-157598 · Jul 13, 2012 · national
Continuity (2)
Division 13939938 · Jul 11, 2013
Related Publication 20160254228A1 · Sep 1, 2016