Reduced resistance source and drain extensions in vertical field effect transistors
View Patent ↗Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.
1. A method for forming a semiconductor device, comprising:
forming semiconductor fins on a semiconductor substrate;
forming a bottom source/drain region in the semiconductor substrate;
forming first charged dielectric spacers on sidewalls of the semiconductor fins;
forming a gate stack over the bottom source/drain region;
forming second charged dielectric spacers on sidewalls of the fin above the gate stack;
recessing the fins to a height below a top level of the second charged dielectric spacers; and
growing a top source/drain region from the recessed fins.
2. The method of claim 1 , further comprising forming a bottom spacer on the bottom source/drain region after forming the first charged dielectric spacers.
3. The method of claim 2 , further comprising etching away material from the first charged dielectric spacers that is above a top level of the bottom spacer.
4. The method of claim 1 , further comprising forming an upper spacer on the gate stack after forming the second charged dielectric spacers.
5. The method of claim 4 , further comprising etching away material from the second charged dielectric spacers that is above a top level of the upper spacer.
6. The method of claim 1 , wherein forming the bottom source/drain region comprises implanting dopants in the semiconductor substrate and annealing the substrate such that dopants diffuse into a lower portion of the fins.
7. The method of claim 1 , wherein recessing the fins comprises recessing the fins to a level above a top surface of the gate stack.
8. The method of claim 1 , wherein the first and second charged dielectric layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.
9. A method for forming a semiconductor device, comprising:
forming semiconductor fins on a semiconductor substrate;
forming a bottom source/drain region in the semiconductor substrate;
forming first charged dielectric spacers on sidewalls of the semiconductor fins;
forming a bottom spacer on the bottom source/drain region after forming the first charged dielectric spacers;
forming a gate stack over the bottom source/drain region;
forming second charged dielectric spacers on sidewalls of the fin above the gate stack;
forming an upper spacer on the gate stack after forming the second charged dielectric spacers;
recessing the fins to a height below a top level of the second charged dielectric spacers; and
growing a top source/drain region from the recessed fins.
10. The method of claim 9 , further comprising etching away material from the first charged dielectric spacers that is above a top level of the bottom spacer.
11. The method of claim 9 , further comprising etching away material from the second charged dielectric spacers that is above a top level of the upper spacer.
12. The method of claim 9 , wherein recessing the fins comprises recessing the fins to a level above a top surface of the gate stack.
13. The method of claim 9 , wherein the first and second charged dielectric layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.
14. A semiconductor device, comprising:
one or more semiconductor fins formed on a semiconductor substrate;
a bottom source/drain region formed in the semiconductor substrate and a bottom portion of the one or more semiconductor fins;
a lower spacer formed above the bottom source/drain region;
first charged dielectric spacers formed on sidewalls of the semiconductor fins;
a gate stack formed above the first charged dielectric spacers and the lower spacer;
second charged dielectric spacers formed on sidewalls of the semiconductor fins above the gate stack; and
a top source/drain region formed above the gate stack and the semiconductor fins.
15. The semiconductor device of claim 14 , wherein the first charged dielectric spacers have a height that is the same as a height of the lower spacer.
16. The semiconductor device of claim 14 , further comprising an upper spacer formed between the gate stack and the top source/drain region.
17. The semiconductor device of claim 16 , wherein the second charged dielectric spacers have a height that is the same as a height of the upper spacer.
18. The semiconductor device of claim 14 , wherein the top source/drain region contacts the semiconductor fins at a height above the gate stack.
19. The semiconductor device of claim 14 , wherein the first and second charged dielectric layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.