MRAM architecture
An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
1. A Magnetorestrictive Random Access Memory (MRAM), comprising:
a first memory cell;
a second memory cell coupled in parallel to said first memory cell, said second memory cell consisting of a first Magnetic Tunnel Junction (MTJ);
a programming line and a bit line adjacent to said second memory cell; and
a third memory cell coupled in series to said first memory cell and said second memory cell.
2. The MRAM of claim 1 , wherein said first memory cell consists of a second MTJ.
3. The MRAM of claim 2 , wherein said third memory cell consists of a third MTJ.
4. The MRAM of claim 3 , further comprising a fourth memory cell coupled to said third memory cell.
5. The MRAM of claim 4 , wherein said fourth memory cell consists of a fourth MTJ.
6. The MRAM of claim 4 , wherein said fourth memory cell is coupled in series with said first memory cell, said second memory cell, and said third memory cell.
7. The MRAM of claim 4 , wherein:
said first memory cell is coupled in parallel to said second memory cell to form a first memory cell group;
a third memory cell is coupled in parallel to said fourth memory cell to form a second memory cell group; and
said first memory cell group is coupled in series with said second memory cell group.
8. A Magnetorestrictive Random Access Memory (MRAM), comprising:
a first memory cell;
a second memory cell coupled in parallel to said first memory cell, said second memory cell including a first Magnetic Tunnel Junction (MTJ) and excluding an isolation device;
a programming line and a bit line adjacent to said second memory cell; and
a third memory cell coupled in series to said first memory cell and said second memory cell.
9. The MRAM of claim 8 , wherein said first memory cell includes a second MTJ and excludes and said isolation device.
10. The MRAM of claim 9 , wherein said third memory cell includes a third MTJ and excludes said isolation device.
11. The MRAM of claim 10 , further comprising a fourth memory cell coupled to said third memory cell.
12. The MRAM of claim 11 , wherein said fourth memory cell includes a fourth MTJ and excludes said isolation device.
13. The MRAM of claim 11 , wherein said fourth memory cell is coupled in series with said first memory cell, said second memory cell, and said third memory cell.
14. The MRAM of claim 11 , wherein:
said first memory cell is coupled in parallel to said second memory cell to form a first memory cell group;
said third memory cell is coupled in parallel to said fourth memory cell to form a second memory cell group; and
said first memory cell group is coupled in series with said second memory cell group.
15. A Magnetorestrictive Random Access Memory (MRAM) comprising:
a first memory cell;
a second memory cell coupled in parallel to said first memory cell, said second memory cell comprising a Magnetic Tunnel Junction (MTJ) and formed without an isolation device; and
a programming line and a bit line adjacent to said second memory cell; and
a third memory cell coupled in series to said first memory cell and said second memory cell.
16. The MRAM of claim 15 , wherein said first memory cell comprises a second MTJ and is formed without said isolation device.
17. The MRAM of claim 16 , wherein said third memory cell comprises a third MTJ and is formed without said isolation device.
18. The MRAM of claim 16 , further comprising a fourth memory cell comprises a fourth MTJ and is formed without said isolation device.
19. The MRAM of claim 18 , wherein said fourth memory cell comprises a fourth MTJ and is formed without said isolation device.
20. The MRAM of claim 18 , wherein said fourth memory cell is coupled in series with said first memory cell.
21. The MRAM of claim 18 , wherein:
said first memory cell is coupled in parallel to said second memory cell to form a first memory cell group;
said third memory cell is coupled in parallel to said fourth memory cell to form a second memory cell group; and
said first memory cell group is coupled in series with said second memory cell group.
22. A Magnetorestrictive Random Access Memory (MRAM) comprising:
a plurality of bit lines;
a first plurality of memory cells adjacent to a first bit line of said plurality of bit lines and each of said first plurality of memory cells consists of a Magnetic Tunnel Junction (MTJ);
a plurality of programming lines, a first programming line of said plurality of programming lines adjacent to at least of said first plurality of memory cells;
a second plurality of memory cells coupled in parallel with said plurality of memory cells, said second plurality of memory cells adjacent to a second bit line of said plurality of bit lines in each of said second plurality of cells consisting of an MTJ;
a first memory cell and a second memory cell of said first plurality of memory cells are coupled in parallel to form a first memory cell group; and
a third memory cell and a fourth memory cell of said first plurality of memory cells are coupled in parallel to form a second memory cell group,
wherein said first memory cell group is coupled in series with said second memory cell group.
23. A Magnetorestrictive Random Access Memory (MRAM) comprising:
a plurality of bit lines;
a first plurality of memory cells adjacent to a first bit line of said plurality of bit lines and each of said first plurality of memory cells consists of a magnetic tunnel junction (MTJ);
a plurality of programming lines, a first programming line of said plurality of programming lines adjacent to at least of said first plurality if memory cells; and
a second plurality of memory cells coupled in series with said first plurality of memory cells, said second plurality of memory cells adjacent to a second bit line of said plurality of bit lines and each of said second plurality of cells consist of said MTJ.