Power management block for use in a non-volatile memory system
View Patent ↗Methods and apparatus for enabling a power up process of a non-volatile memory to occur efficiently are disclosed. According to one aspect of the present invention, a method for utilizing a memory system that has a non-volatile memory with at least one reserved memory area includes providing power to the memory system, initializing the non-volatile memory, and writing a first signature into the reserved memory area. The first signature is arranged to indicate that the memory system was successfully initialized. In one embodiment, the method also includes executing a power down process on the memory system, and writing a second signature into the reserved memory area which indicates that the power down process has been executed.
1. A method for utilizing a memory system, the memory system including a non-volatile memory, the non-volatile memory including at least one reserved memory area, the method comprising:
providing power to the memory system;
determining when the memory system has previously undergone a substantially normal power down process;
performing a first process on the non-volatile memory when it is determined that the memory system has not previously undergone a normal power down process, the first process being arranged to ready the non-volatile memory for use; and
substantially enabling the non-volatile memory to be used when it is determined that the memory system has previously undergone a normal power down process.
2. The method of claim 1 wherein substantially enabling the non-volatile memory to be used includes writing a first signature into the at least one reserved memory area to indicate that the non-volatile memory is substantially enabled.
3. The method of claim 1 wherein determining when the memory system has previously undergone the substantially normal power down process includes:
determining when the at least one reserved memory area includes a first signature, the first signature being arranged to indicate that the normal power down process has previously occurred.
4. The method of claim 3 wherein determining when the memory system has previously undergone the substantially normal power down process further includes:
determining when the at least one reserved memory area includes a second signature, the second signature being arranged to indicate that the memory system has previously undergone an initialization process.
5. The method of claim 4 wherein when it is determined that the at least one reserved memory area does not include the second signature and does not include the first signature, the first process is the initialization process.
6. The method of claim 4 wherein when it is determined that the at least one reserved memory area includes the second signature and does not include the first signature, the first process is a data recovery process.
7. The method of claim 6 wherein the data recovery process is arranged to reclaim memory within the non-volatile memory.
8. The method of claim 7 wherein the data recovery process includes at least one of completing a file copying process and resolving physical blocks associated with the non-volatile memory.
9. The method of claim 1 wherein the first process is one of a data recovery process and a memory initialization process.
10. The method of claim 1 wherein the non-volatile memory is a NAND flash memory.
11. A memory system comprising:
a non-volatile memory, the non-volatile memory including at least one reserved memory area;
means for providing power to the memory system;
means for determining when the memory system has previously undergone a substantially normal power down process;
means for performing a first process on the non-volatile memory when it is determined that the memory system has not previously undergone a normal power down process, the first process being arranged to ready the non-volatile memory for use; and
means for substantially enabling the non-volatile memory to be used when it is determined that the memory system has previously undergone a normal power down process.
12. The memory system of claim 11 wherein the means for substantially enabling the non-volatile memory to be used include means for writing a first signature into the at least one reserved memory area to indicate that the non-volatile memory is substantially enabled.
13. The memory system of claim 11 wherein the means for determining when the memory system has previously undergone the substantially normal power down process include:
means for determining when the at least one reserved memory area includes a first signature, the first signature being arranged to indicate that the normal power down process has previously occurred.
14. The memory system of claim 13 wherein the means for determining when the memory system has previously undergone the substantially normal power down process further include:
means for determining when the at least one reserved memory area includes a second signature, the second signature being arranged to indicate that the memory system has previously undergone an initialization process.
15. The memory system of claim 14 wherein when it is determined that the at least one reserved memory area does not include the second signature and does not include the first signature, the first process is the initialization process.
16. The memory system of claim 14 wherein when it is determined that the at least one reserved memory area includes the second signature and does not include the first signature, the first process is a data recovery process.
17. A memory system comprising:
code devices that cause a determination of when the memory system has previously undergone a substantially normal power down process;
code devices that are arranged to cause a first process to be performed on a non-volatile memory associated with the memory system when it is determined that the memory system has not previously undergone a normal power down process, wherein the first process is arranged to ready the non-volatile memory for use;
code devices that are arranged to cause the non-volatile memory to be enabled for use when it is determined that the memory system has previously undergone a normal power down process; and
a memory area that stores the code devices.
18. The memory system of claim 17 wherein the code devices that are arranged to cause the non-volatile memory to be enabled for use include code devices that are arranged to write a first signature into at least one reserved memory area of the non-volatile memory to indicate that the non-volatile memory is enabled for use.
19. The memory system of claim 17 wherein the code devices that cause the determination of when the memory system has previously undergone the substantially normal power down process include:
code devices that are arranged to cause a determination of when at least one reserved memory area of the non-volatile memory includes a first signature, the first signature being arranged to indicate that the normal power down process has previously occurred.
20. The memory system of claim 19 wherein the code devices that cause the determination of when the memory system has previously undergone the substantially normal power down process further include:
code devices that are arranged to cause a determination of when the at least one reserved memory area includes a second signature, the second signature being arranged to indicate that the memory system has previously undergone an initialization process.
21. The memory system of claim 20 wherein when it is determined that the at least one reserved memory area does not include the second signature and does not include the first signature, the first process is the initialization process.
22. The memory system of claim 20 wherein when it is determined that the at least one reserved memory area includes the second signature and does not include the first signature, the first process is a data recovery process.
23. A memory system comprising:
a non-volatile memory; and
a control device, the control device being arranged to determine when the memory system has previously undergone a substantially normal power down process, to perform a first process on the non-volatile memory when it is determined that the memory system has not previously undergone a normal power down process wherein the first process is arranged to ready the non-volatile memory for use, and to substantially enable the non-volatile memory to be used when it is determined that the memory system has previously undergone a normal power down process.
24. The memory system of claim 23 wherein the first process is one of a data recovery process and a memory initialization process.
25. The system of claim 23 wherein the non-volatile memory is a NAND flash memory.