Architecture for routing resources in a field programmable gate array

1. An architecture for routing channels in a field programmable gate array, comprising:

a first plurality of routing channels having a first direction;

a second plurality of routing channels having a second direction, said first plurality of routing channels intersecting said second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in said routing channels;

a first number of reprogrammable elements disposed at intersections in a first one of said plurality of matrices, said first number of reprogrammable elements disposed on said intersecting interconnect conductors in a first pattern;

a second number of reprogrammable elements disposed at intersections in a second one of said plurality of matrices, said second number of reprogrammable elements greater than said first number of reprogrammable elements, and said second number of reprogrammable elements disposed on said intersecting interconnect conductors in a second pattern distinct from said first pattern;

a third number of reprogrammable elements disposed at intersections in a third one of said plurality of matrices, said third number of reprogrammable elements greater than said second number of reprogrammable elements, and said third number of reprogrammable elements disposed on said intersecting interconnect conductors in a third pattern distinct from said first pattern and said second pattern; and

a plurality of logic blocks coupled to one another through said first plurality of routing channels and said second plurality of routing channels, wherein each one of said plurality of logic blocks comprises a plurality of clusters, each one of said plurality of logic clusters comprising two three-input lookup tables each having an output, one two-input lookup table having an output, and a D flip-flop having an input and an output.

2. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal pattern.

3. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal minus one pattern.

4. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal minus two pattern.

5. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal minus three pattern.

6. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal plus one pattern.

7. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal plus two pattern.

8. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a diagonal plus three pattern.

9. The architecture of claim 1 , wherein one of said first number, said second number and said third number of reprogrammable elements are disposed on said intersecting interconnect conductors in a fully populated pattern.

10. The architecture of claim 1 , wherein said outputs of said two three-input lookup tables are multiplexed to said input and said output of said D flip-flop.