Self-boosting system with suppression of high lateral electric fields
View Patent ↗In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.
1. An apparatus for programming a memory system, said system comprising strings of charge storage transistors for storing different charge states, said strings including a first and a second string each connected between one of a plurality of bit lines and a source line and controlled by common word lines, said apparatus comprising:
a circuit programming the system by applying a program voltage to the word lines, one selected word line at a time, to program all of the transistors in the first string;
said circuit coupling, during the programming, first boosting voltage level(s) to at least some of the transistors in the second string between said selected word line and said one bit line connected to the second string to boost electrical potential(s) of channel regions of transistors in the second string to a value or values closer to the program voltage to reduce program disturb; and
said circuit coupling, during the programming, a second voltage level that is less than the first voltage level(s) to at least one isolation charge storage transistor having a source and drain in the second string between the selected word line and the source line, said second voltage level being such that a first channel area of the second string on the source side of the at least one isolation transistor is electrically isolated from a second channel area of the second string on the drain side of the at least one isolation transistor, so that the at least one isolation transistor is at a plurality of positions separated from the selected word line during the programming;
wherein when the selected word line is at a first position at a first distance from said one bit line and at a second position at a second distance smaller than the first distance from said one bit line at two different times, the coupling is such that the position of the at least one isolation transistor is separated from the second position by a larger number of word lines than from the first position, to reduce program disturb, and such that the position of the at least one isolation transistor is separated from the first and second positions by at least one word line.
2. The apparatus of claim 1 , wherein the second position is closer to the one bit line than to the source line.
3. The apparatus of claim 1 , wherein the second distance is not more than about 15% of a distance between the source line and said one bit line.
4. The apparatus of claim 1 , wherein the circuit programs the system by applying the program voltage to the word lines sequentially from the word lines located near the source line to those located near said one bit line, so that the selected word line is at positions at decreasing distances from said one bit line as the programming progresses.
5. The apparatus of claim 4 , wherein position of the at least one isolation transistor is substantially stationary when the programming applies the program voltage sequentially to the word lines located between such bit line and a predetermined location between the source line and said one bit line.
6. The apparatus of claim 5 , wherein the predetermined location is at a distance from said one bit line that is not more than about 15% of a distance between the source line and said one bit line.
7. The apparatus of claim 1 , wherein the circuit programs the system by applying the program voltage to the word lines sequentially from the word lines located near the source line to those located near said one bit line, so that the selected word line is at positions at decreasing distances from said one bit line as the programming progresses, and wherein position of the at least one isolation transistor is not stationary when the programming applies the program voltage sequentially to the word lines located between the one bit line and the predetermined location.
8. The apparatus of claim 7 , wherein position of the at least one isolation transistor moves towards the one bit line by one word line when the selected word line moves towards the one bit line by every one word line when the programming applies the program voltage sequentially to the word lines located between the source line and the predetermined location.
9. The apparatus of claim 1 , wherein the circuit programs the system by applying the program voltage to the word lines sequentially from the word lines located near the source line to those located near said one bit line, so that the selected word line is at positions at decreasing distances from said one bit line as the programming progresses, and wherein position of the isolation transistor moves towards the one bit line by one word line when the selected word line moves towards the one bit line by every n word lines when the programming applies the program voltage sequentially to the word lines located between said one bit line and a predetermined location between the source line and said one bit line, n being a positive integer greater than 1.
10. The apparatus of claim 9 , wherein the predetermined location is at a distance from said one bit line that is not more than about 15% of a distance between the source line and said one bit line.
11. The apparatus of claim 1 , wherein the at least one isolation transistor is at position(s) separated from the selected word line by at least one separation word line when the programming applies the program voltage sequentially to the word lines.
12. The apparatus of claim 11 , wherein the circuit couples third voltage level(s) to the at least one separation word line, wherein the third voltage level(s) is such that a portion of the second channel area extending between the isolation transistor and the selected word line remains electrically conductive, and such that the electrical potential of a channel region of such portion is not boosted.
13. The apparatus of claim 12 , wherein at least one of the third voltage level is between about 3V and said first boosting voltage level(s).
14. The apparatus of claim 11 , wherein the circuit couples at least one of the third voltage level(s) to at least one separation word line, wherein the at least one third voltage level(s) is such that electrical potential(s) of a portion of the second channel area extending between the isolation transistor and the selected word line is boosted to a value or values closer to the program voltage to reduce program disturb.
15. The apparatus of claim 14 , wherein at least one of the third voltage level is between about 3V and said program voltage.
16. The apparatus of claim 1 , wherein the circuit programs the system by applying the program voltage to the word lines sequentially from the word lines located near the source line to those located near said one bit line, so that the selected word line is at positions at decreasing distances from said one bit line as the programming progresses, and wherein the number of word lines separating the isolation transistor and the selected word line increases as the programming progresses towards said one bit line from a predetermined location between the source line and said one bit line.
17. The apparatus of claim 16 , wherein the number of word lines separating the isolation transistor and the selected word line, if any, remains substantially constant as the programming progresses from word lines adjacent to the source line to said predetermined location.
18. The apparatus of claim 16 , wherein the predetermined location is at a distance from said one bit line that is not more than about 15% of a distance between the source line and said one bit line.