Semiconductor device and programming method therefor
View Patent ↗A semiconductor device includes bit lines ( 14 ) provided in a semiconductor substrate ( 10 ), word lines ( 16 ) provided above the bit lines and running in a width direction of the bit lines ( 14 ), metal lines ( 22 ) provided above the word lines ( 16 ) and running in a length direction of the bit lines ( 14 ), and bit line contact regions ( 28 ) running in the length direction of the word lines ( 16 ) and located between word line regions ( 26 ) in which a plurality of word lines ( 16 ) are disposed. Each of the bit lines ( 14 ) is connected with every other metal line ( 22 ) in the bit line contact regions ( 28 ). It is thus possible to provide a semiconductor device and a fabrication method therefor in which an alignment margin can be ensured between a contact hole ( 18 ) and the bit line ( 14 ) to enable downsizing of a memory cell.
1. A semiconductor device comprising:
bit lines provided in a semiconductor substrate;
word lines provided above the bit lines and running in a width direction of the bit lines;
metal lines provided above the word lines and running in a length direction of the bit lines; and
bit line contact regions running in the length direction of the word lines and located between word line regions in which a plurality of word lines are disposed, wherein each of the bit lines is connected only with every other metal line in the bit line contact regions, and wherein each of the bit lines has a contact pad wider in the bit line contact region at positions where the bit lines are connected with the metal lines than a width of the bit line in the word line regions.
2. The semiconductor device as claimed in claim 1 , wherein contact pads adjacent to each other in the width direction of the bit lines are electrically isolated from each other.
3. The semiconductor device as claimed in claim 2 , wherein the adjacent contact pads are electrically isolated from each other by a trench isolation region.
4. The semiconductor device as claimed in claim 1 , wherein the metal lines not connected to the bit lines in a first bit line contact region are connected to the bit lines in a second bit line contact region, the word line regions being respectively interposed between the first bit line contact region and the second bit line contact region.
5. The semiconductor device as claimed in claim 1 , wherein the bit lines adjacent to each other in the length direction of the bit lines are electrically isolated from each other.
6. The semiconductor device as claimed in claim 5 , wherein the adjacent bit lines are electrically isolated from each other by a trench isolation region.
7. The semiconductor device as claimed in claim 1 , wherein two of the bit lines connected to a transistor provided in the word line region are each respectively connected to adjacent metal lines in the bit line contact region provided at both sides of the word line region.
8. The semiconductor device as claimed in claim 1 , wherein:
the bit lines have source regions and drain regions; and
the word lines have gate electrodes provided on an ONO film formed on the semiconductor substrate.
9. A method of fabricating a semiconductor device comprising the steps of:
forming bit lines in a semiconductor substrate;
forming word lines above the bit lines and running in a width direction of the bit lines;
forming metal lines above the word lines and running in a length direction of the bit lines; and
forming bit line contact regions running in the length direction of the word lines to be located between word line regions in which a plurality of word lines are disposed, wherein the step of forming the bit lines includes the step of forming a contact pad as a portion of each of the bit lines for connecting the bit lines to the metal lines in the bit line contact regions, the contact pads of the bit lines being formed wider in the bit line contact regions than the bit lines in the word line regions, and wherein the step of forming the metal lines comprises the step of connecting each of the bit lines only with every other metal line in the bit line contact regions.
10. The method as claimed in claim 9 , further comprising the step of forming a trench isolation region between regions in which adjacent contact pads are to be formed.
11. The method as claimed in claim 10 , wherein the step of forming the bit lines comprises the step of implanting ions in regions in which the bit lines and the contact pads of the bit lines are to be formed and in the regions that are adjacent to the bit lines in the trench isolation regions.
12. The method as claimed in claim 9 , further comprising the step of forming an ONO film on the semiconductor substrate,
wherein the step of forming word lines comprises forming word lines including gate electrodes on the ONO film.