Granted Patent B2

US 7,783,693 · App. 11/442,971 · Granted Aug 24, 2010

Abstract

Claims (30)

1. A reconfigurable circuit comprising:

a plurality of processing elements, each of the processing elements includes an arithmetic unit respectively;

a sequencer to control an operation of the arithmetic unit; and

a network connected to the plurality of processing elements,

the processing element includes,

a first arithmetic unit to perform addition or subtraction of a first input data and a second input data and outputting output data; and

a first selector to select the output data of the first arithmetic unit or a third input data,

a second selector to select the selected data by the first selector in counter mode and a fourth input data in ALU mode, and to output the selected one as the first input data to the first arithmetic unit, and

a third selector to select a step size of a counter in counter mode and a fifth input data in ALU mode, and to output the selected one as the second input data to the first arithmetic unit,

wherein the first selector selects, in the counter mode, the third input data as an initial value at initial time, in other cases selects the output data of the first arithmetic unit, and outputs the selected one to the second selector.

2. The reconfigurable circuit according to claim 1 further comprising:

a fourth selector to select a first step size or a second step size, and outputting the selected one as the step size of the counter to the third selector.

3. The reconfigurable circuit according to claim 1 , wherein the sequencer generates a fetch enable signal and an address, and the reconfigurable circuit further comprising:

a configuration memory storing configuration data;

a configuration register storing the configuration data read out from the configuration memory in response to the fetch enable signal and the address;

a control section controlling the first to third selectors in accordance with the configuration data to be stored in the configuration register; and

an output control section controlling output timing of output data of the first arithmetic unit,

wherein the first arithmetic unit, the configuration register, the control section, and the output control section compose a first processing element.

4. The reconfigurable circuit according to claim 3 , wherein the control section initiates, in the counter mode, the first arithmetic unit as the counter with the fetch enable signal as a trigger.

5. The reconfigurable circuit according to claim 3 , wherein the configuration register has a register which stores an interval time between respective output data of the first arithmetic unit, and the output control section controls output timing of output data of the first arithmetic unit in response to the interval time.

6. The reconfigurable circuit according to claim 3 further comprising:

a second processing element outputting a valid signal to the first processing element, wherein the control section within the first processing element initiates the first arithmetic unit as the counter with the valid signal as a trigger.

7. The reconfigurable circuit according to claim 3 further comprising:

a second processing element outputting a valid signal to the first processing element, wherein the output control section within the first processing element controls output timing of each output data of the first arithmetic unit in response to the valid signal.

8. The reconfigurable circuit according to claim 3 further comprising:

a second processing element generating a predicate signal in accordance with computing result of a second arithmetic unit, wherein the first processing element starts or stops, in counter mode, operation as the counter in response to the predicate signal.

9. The reconfigurable circuit according to claim 8 , wherein when the operation stop of the counter is directed by the predicate signal, the first processing element stops operation as the counter until the fetch enable signal is input.

10. The reconfigurable circuit according to claim 3 further comprising:

a second processing element generating a fifth input data, wherein the configuration register includes: a step size register for storing a step size of the counter; an initial value register for storing the third input data as the initial value; and a rewrite setting register for storing the data which indicates permission of rewriting the data of the step size register or the initial value register, and wherein the first processing element includes a rewrite control section which rewrites the step size register or the initial value register in accordance with the fifth input data, only when the rewrite setting register stores the data which permits rewriting.

11. The reconfigurable circuit according to claim 10 , wherein the rewrite control section rewrites the step size register or the initial value register in accordance with the fifth input data, even though the fetch enable signal is not input.

Assignments (12)