IP Library Granted Patent US 7,496,870
Granted Patent B2
US 7,496,870 · App. 11/551,573 · Granted Feb 24, 2009

Method of selecting cells in logic restructuring

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Quick Facts
Patent No.
US 7,496,870
App. No.
11/551,573
Granted
Feb 24, 2009
Kind
B2
Abstract

The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Claims (40)

1. A method of selecting cells in an integrated circuit design suitable for use in logic restructuring of an original design, wherein the original design includes a set of parameters, the method comprising:

(a) forming a restructuring set having restructuring cells including at least an initial cell, wherein the restructuring set is adapted to accept additional cells identified as restructuring cells;

(b) forming a candidate set adapted to include candidate cells, wherein each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set,

(c) removing a selected candidate cell from the candidate set;

(d) for each restructuring cell connected to the selected candidate cell, identifying a corresponding cell pair parameter for a cell pair formed by that restructuring cell and the selected candidate cell;

(e) if the cell pair parameter is included in the set of parameters, then placing the removed, selected candidate cell into the restructuring set as an identified restructuring cell and placing at least one cell that is connected to the removed, selected candidate cell into the candidate set;

(f) repeating steps (c) through (e) for other candidate cells in the candidate set; and

(g) returning a completed restructuring set.

2. The method of claim 1 wherein step (f) comprises repeating steps (c)through (e) until a size of the restructuring set has reached a limit or the candidate set includes no candidate cells.

3. The method of claim 1 wherein the cell pair parameter comprises at least one of a cell type or a pin number.

4. The method of claim 3 wherein the set of parameters includes a set cell pair parameters corresponding to cell pairs formed in the design, wherein each cell pair parameter comprises an output cell type, output pin number, input pin number and input cell type.

5. The method of claim 4 wherein the set of cell pair parameters includes cell pair parameters from at least one symmetrical design.

6. The method of claim 1 and further comprising placing bounded cells into the restructuring set as restructuring cells wherein a bounded cell is a cell that is not identified as a restructuring cell when step (f) is complete and all inputs and all outputs of that cell are connected to identified restructuring cells.

7. The method of claim 1 wherein the candidate cells in the candidate set are exclusive of the restructuring cells in the restructuring set.

8. The method of claim 1 and further comprising, before step (c):

(h) identify cell pairs that are directly connected to one another in the original design;

(i) for each of the pairs identified in step (h):

(i)(1) defining a cell pair parameter for that cell pair, which includes an output cell type, and output pin number, an input pin number and an input cell type,

(i)(2) if the cell pair parameter is not already in the set of parameters, placing the cell pair parameter in the set of parameters;

(j) repeat steps (h) and (i) for a symmetric design that is symmetric to the original design.

9. A computer-readable medium having a set of computer-executable instructions, which when executed by a computer perform a method for selecting cells in an integrated circuit suitable for use in logic restructuring of an original design, wherein the original design includes a set of parameters, the method comprising:

(a) forming a restructuring set having restructuring cells including at least an initial cell, wherein the restructuring set is adapted to accept additional cells identified as restructuring cells;

(b) forming a candidate set adapted to include candidate cells, wherein each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set,

(c) removing a selected candidate cells from the candidate set;

(d) for each restructuring cell connected to the selected candidate cell, identifying a corresponding cell pair parameter for a cell pair formed by that restructuring cell and the selected candidate cell;

(e) if the cell pair parameter is included in the set of parameters, then placing the removed, selected candidate cell into the restructuring set as an identified restructuring cell and placing at least one cell that is connected to the removed, selected candidate cell into the candidate set:

(f) repeating steps (c) through (e) for other candidate cells in the candidate set; and

(g) returning a completed restructuring set.

10. The computer-readable medium of claim 9 wherein the instructions are executable on a general purpose computer.

11. The computer-readable medium of claim 9 wherein step (f) comprises repeating steps (c) through (e) until a size of the restructuring set has reached a limit or the candidate set includes no candidate cells.

12. The computer-readable medium of claim 9 wherein cell pair parameter comprises at least one of a cell type or a pin number.

13. The computer-readable medium of claim 12 wherein the set of parameters includes a set of cell pair parameters corresponding to cell pairs formed in the design, wherein each cell pair parameter comprises an output cell type, output pin number, input pin number and input cell type.

14. The computer-readable medium of claim 9 , wherein the method further comprises placing bounded cells into the restructuring set as restructuring cells, wherein a bounded cell is a cell that is not identified as a restructuring cell when step (f) is complete and all inputs and all outputs of that cell are connected to identified restructuring cells.

15. The computer-readable medium of claim 9 , wherein the candidate cells in the candidate set are exclusive of the restructuring cells in the restructuring set.

16. The computer-readable medium of claim 9 , wherein the method further comprises, before step (c):

(h) identify cell pairs that are directly connected to one another in the original design;

(i) for each of the pairs identified in step (h):

(i)(1) defining a cell pair parameter for that cell pair, which includes an output cell type, and output pin number, an input pin number and an input cell type,

(i)(2) if the cell pair parameter is not already in the set of parameters, placing the cell pair parameter in the set of parameters;

(j) repeat steps (h) and (i) for a symmetric design that is symmetric to the original design.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →