Solder bump confinement system for an integrated circuit package
View Patent ↗A solder bump confinement system is provided including providing a substrate, patterning a contact material on the substrate, depositing an inner passivation layer over the contact material and the substrate, forming an under bump material defining layer over the contact material by sputtering, and forming a system interconnect over the contact material and on the under bump material defining layer.
1. A method of manufacturing a solder bump confinement system comprising:
providing a substrate;
patterning a contact material on the substrate;
depositing an inner passivation layer over the contact material and the substrate;
patterning an under bump material pad over the contact material;
forming an under bump material defining layer, having a bump opening contained therein, directly on the under bump material pad; and
forming a system interconnect over the contact material including coupling the system interconnect on the under bump material defining layer and the under bump material pad through the bump opening.
2. The method as claimed in claim 1 further comprising depositing an adhesion layer on the contact material and the inner passivation layer by sputtering.
3. The method as claimed in claim 1 in further comprising sputtering a seed layer between the contact material and the under bump material defining layer.
4. The method as claimed in claim 1 further comprising sputtering a barrier layer between the contact material and the under bump material defining layer.
5. The method as claimed in claim 1 further comprising forming an outer passivation layer on the under bump material defining layer and the inner passivation layer.
6. A method of manufacturing a solder bump confinement system comprising:
providing a substrate in which the substrate includes a semiconductor wafer, a MEMS wafer, or a printed circuit board;
patterning a contact material on the substrate;
depositing an inner passivation layer over the contact material and the substrate;
patterning an under bump material pad over the contact material;
forming an under bump material defining layer, having a bump opening contained therein, directly on the under bump material pad including the under bump material defining layer having a thickness in the range of 200 Angstrom to 1500 Angstrom; and
forming a system interconnect over the contact material including coupling the system interconnect on the under bump material defining layer and the under bump material pad through the bump opening.
7. The method as claimed in claim 6 further comprising depositing an adhesion layer on the contact material and the inner passivation layer by sputtering including the adhesion layer having the thickness in the range of 200 Angstrom to 1500 Angstrom.
8. The method as claimed in claim 6 in further comprising sputtering a seed layer between the contact material and the under bump material defining layer including the seed layer having the thickness in the range of 1000 Angstrom to 8000 Angstrom.
9. The method as claimed in claim 6 further comprising sputtering a barrier layer between the contact material and the under bump material defining layer including the barrier layer having the thickness in the range of 800 Angstrom to 3000 Angstrom.
10. The method as claimed in claim 6 further comprising sputtering an adhesion layer, a barrier layer, and a seed layer between the contact material and the under bump material defining layer for achieving a low temperature process.