SRAM bus architecture and interconnect to an FPGA
View Patent ↗An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.
1. An architecture for a programmable integrated circuit including:
a first group of logic function modules associated with a first group of FPGA routing conductors;
a second group of logic function modules spaced apart from said first group of logic function modules and associated with a second group of FPGA routing conductors;
a plurality of dedicated SRAM blocks, each SRAM block having address busses, data busses and control lines;
a plurality of pass-through interconnect conductors spanning each SRAM block, each of said plurality of said pass-through interconnect conductors having a first end and a second end;
a first plurality of user-programmable interconnect elements coupled between first ends of the pass-through interconnect conductors and ones of the first group of FPGA routing conductors;
a second plurality of user-programmable interconnect elements coupled between second ends of the pass-through interconnect conductors and ones of the second group of FPGA routing conductors;
a multi-conductor address bus disposed in one of said plurality of dedicated SRAM blocks forming first intersections with said plurality of pass-through interconnect conductors;
a multi-conductor data bus disposed in one of said plurality of dedicated SRAM blocks forming second intersections with said plurality of pass-through interconnect conductors;
a multi-conductor group of control signal lines disposed in one of said plurality of dedicated SRAM blocks forming third interconnect intersections with said plurality of pass-through interconnect conductors; and
user-programmable interconnect elements disposed at selected ones of said first, second and third intersections.
2. The architecture of claim 1 wherein:
the plurality of dedicated SRAM blocks includes a first SRAM block and a second SRAM block;
a first edge of the first SRAM block and a first edge of the second SRAM block are each adjacent to different ones of the groups of logic function modules;
a second edge of the first SRAM block is adjacent to a second edge of the second SRAM block;
the plurality of pass-through interconnect conductors span the first and second SRAM blocks and run perpendicular to the first edge of the first SRAM block and the first edge of the second SRAM block;
a plurality of SRAM address, data, and control lines of the first SRAM block and a plurality of SRAM address, data, and control lines of the second SRAM block traverse each of the first and second SRAM blocks in a direction perpendicular to and forming intersections with the plurality of pass-through interconnect conductors;
a third plurality of user-programmable interconnect elements disposed between at least one of the plurality of SRAM address, data, and control lines of the first SRAM block and at least one of the SRAM address, data, and control lines of the second SRAM block; and
a fourth plurality of user-programmable interconnect elements disposed between at least one of the pass-through interconnect conductors and at least one of the plurality of SRAM address, data, and control lines of said first SRAM block and the plurality of SRAM address, data, and control lines of the second SRAM block.
3. The architecture of claim 2 wherein the user-programmable interconnect elements comprise a tri-statable buffer disposed in parallel with a pass transistor.
4. The architecture of claim 2 wherein the user-programmable interconnect elements comprise MOS pass-transistor.
5. The architecture of claim 2 wherein intersections of the SRAM address, data, and control lines and the pass-through interconnect conductors are less than fully populated with user-programmable interconnect elements.
6. The architecture of claim 1 wherein:
the plurality of SRAM blocks are organized into groups; and
a plurality of SRAM address, data, and control lines of a first SRAM block and a plurality of SRAM address, data, and control lines of a second SRAM block within each group traverse each of the first and second SRAM blocks in the group in a direction perpendicular to and forming intersections with the plurality of pass-through interconnect conductors;
a third plurality of user-programmable interconnect elements disposed between at least one of the plurality of SRAM address, data, and control lines of the first SRAM block and at least one of the SRAM address, data, and control lines of the second SRAM block in each group; and
a fourth plurality of user-programmable interconnect elements disposed between at least one of the pass-through interconnect conductors and at least one of the plurality of SRAM address, data, and control lines of said first SRAM block and the plurality of SRAM address, data, and control lines of the second SRAM block in each group.
7. The architecture of claim 6 wherein a plurality of the groups of SRAM blocks are disposed together defining an area that divides a first at least two adjacent groups of logic function modules from a second at least two adjacent groups of logic function modules.
8. The architecture of claim 1 , wherein each SRAM block further includes:
a plurality of write-enable lines, each write-enable line coupled to one input of a write-enable AND gate through a write-enable polarity-control element controlled by a write-enable polarity-control bit, an output of the write-enable AND gate coupled to a write enable control line; and
a plurality of read-enable lines, each rea -enable line coupled to one input of a read -enable AND gate through a read-enable polarity-control element controlled by a read-enable polarity-control bit, an output of the read-enable AND gate coupled to a read enable control line.