Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
View Patent ↗A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over a top surface of the substrate;
forming a resistive layer over the substrate and the first conductive layer;
forming a dielectric layer over the substrate, first conductive layer and resistive layer;
forming a first passivation layer over the dielectric layer;
removing first and second separate portions of the first passivation layer to expose first and second portions of the dielectric layer;
forming a second conductive layer in direct contact with the first portion of the dielectric layer after forming the first passivation layer, wherein the dielectric layer, resistive layer, first conductive layer, and second conductive layer operate as a capacitor;
etching a first opening in the second portion of the dielectric layer as defined by the removed second separate portion of the first passivation layer to expose a surface of the resistive layer;
forming a third conductive layer over the second conductive layer and a portion of the first passivation layer;
forming a fourth conductive layer over the third conductive layer; and
forming a second passivation layer over the fourth conductive layer and first passivation layer.
2. The method of manufacturing of claim 1 , further including:
removing a portion of the second passivation layer to expose the fourth conductive layer;
forming a fifth conductive layer over of the fourth conductive layer in the removed portion of the second passivation layer; and
forming a sixth conductive layer over the fourth conductive layer to provide electrical connectivity.
3. The method of manufacturing of claim 2 , wherein the fifth and sixth conductive layers operate as an under-bump metallurgy (UBM) structure to provide electrical connectivity.
4. The method of manufacturing of claim 2 , further including forming a bump over the sixth conductive layer to provide electrical connectivity.
5. The method of manufacturing of claim 4 , wherein the bump further comprises a solder bump, gold (Au) bump, or a copper (Cu) pillar structure.
6. The method of manufacturing of claim 1 , further including forming a wire-bonding (WB) pad over the substrate.
7. The method of manufacturing of claim 6 , further including forming the second conductive layer over the WB pad.
8. The method of manufacturing of claim 7 , wherein the second passivation layer terminates on a portion of the first passivation layer or on a portion of the second conductive layer over the WB pad.
9. The method of manufacturing of claim 1 , wherein a dimension of the second conductive layer is defined by a lithography of the first passivation layer to limit over etching of the second conductive layer.
10. The method of manufacturing of claim 1 , wherein the first passivation layer is used as a hard mask to etch the first opening in the dielectric layer.
11. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a resistive layer over a portion of the first conductive layer;
forming a dielectric layer over the resistive layer;
forming a first passivation layer over the dielectric layer, first conductive layer, and substrate;
removing first and second separate portions of the first passivation layer to expose first and second portions of the dielectric layer;
forming a second conductive layer over the first portion of the dielectric layer after forming the first passivation layer; and
etching a first opening in the second portion of the dielectric layer as defined by the removed second separate portion of the first passivation layer to expose a surface of the resistive layer.
12. The method of claim 11 , further including:
forming a third conductive layer over the second conductive layer and a portion of the first passivation layer;
forming a fourth conductive layer over the third conductive layer; and
forming a second passivation layer over the fourth conductive layer and first passivation layer.
13. The method of claim 12 , further including:
removing a portion of the second passivation layer to expose the fourth conductive layer;
forming a fifth conductive layer over the fourth conductive layer; and
forming a sixth conductive layer over the fifth conductive layer.
14. The method of claim 13 , wherein the fifth and sixth conductive layers operate as an under-bump metallurgy structure to provide electrical connectivity.
15. The method of claim 13 , further including forming a bump formed over the sixth conductive layer to provide electrical connectivity.
16. The method of claim 11 , wherein the dielectric layer, resistive layer, first conductive layer, and second conductive layer operate as a capacitor.
17. The method of claim 11 , wherein a dimension of the second conductive layer is defined by a lithography of the first passivation layer to limit over etching of the second conductive layer.
18. The method of claim 11 , wherein the removed second separate portion of the first passivation layer is used as a hard mask to etch the first opening in the dielectric layer.
19. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a resistive layer over a portion of the first conductive layer;
forming a dielectric layer over the resistive layer;
forming a first passivation layer over the dielectric layer;
removing a first portion of the first passivation layer to expose a first portion of the dielectric layer; and
forming a second conductive layer over the first portion of the dielectric layer after forming the first passivation layer.
20. The method of claim 19 , further including:
removing a second portion of the first passivation layer separate from the first portion of the first passivation layer to expose a second portion of the dielectric layer; and
etching a first opening in the second portion of the dielectric layer as defined by the removed second portion of the first passivation layer to expose a surface of the resistive layer.
21. The method of claim 20 , further including:
forming a third conductive layer over the second conductive layer and a portion of the first passivation layer;
forming a fourth conductive layer over the third conductive layer; and
forming a second passivation layer over the fourth conductive layer and first passivation layer.
22. The method of claim 21 , further including:
removing a portion of the second passivation layer to expose the fourth conductive layer;
forming a fifth conductive layer over the fourth conductive layer; and
forming a sixth conductive layer over the fifth conductive layer.
23. The method of claim 19 , wherein the dielectric layer, resistive layer, first conductive layer, and second conductive layer operate as a capacitor.
24. The method of claim 19 , wherein a dimension of the second conductive layer is defined by a lithography of the first passivation layer to limit over etching of the second conductive layer.
25. The method of claim 19 , wherein the removed second portion of the first passivation layer is used as a hard mask to etch the first opening in the dielectric layer.