IP Library Granted Patent US 7,750,452
Granted Patent B2
US 7,750,452 · App. 11/768,869 · Granted Jul 6, 2010

Same size die stacked package having through-hole vias formed in organic material

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Quick Facts
Patent No.
US 7,750,452
App. No.
11/768,869
Granted
Jul 6, 2010
Kind
B2
Abstract

A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.

Claims (47)

1. A semiconductor package, comprising:

a substrate or leadframe structure;

a plurality of stacked same-size interconnected dies disposed over the substrate or leadframe structure, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

a plurality of bond pads formed on the top surface of each of the stacked same-size interconnected dies;

a plurality of conductive traces formed on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs; and

an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of stacked same-size interconnected dies.

2. The semiconductor package of claim 1 , wherein the first die of the plurality of stacked same-size interconnected dies is wire-bonded to the substrate or leadframe structure.

3. The semiconductor package of claim 2 , further including a wire coupled between the substrate or leadframe structure and a terminal land.

4. The semiconductor package of claim 1 , further including a conductive lid disposed over a surface of the substrate or leadframe structure.

5. The semiconductor package of claim 4 , wherein the first die of the plurality of stacked same-size interconnected dies is attached to the conductive lid using a die attach adhesive material.

6. The semiconductor package of claim 1 , wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

7. The semiconductor package of claim 1 wherein the plurality of conductive THVs surround the periphery of each die.

8. A semiconductor package, comprising:

a substrate or leadframe structure having an integrated cavity;

a plurality of stacked same-size interconnected dies disposed within the integrated cavity, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

a plurality of bond pads formed on the top surface of each of the stacked same-size interconnected dies;

a plurality of conductive traces formed on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs;

a bond wire coupled between the second die of the stacked same-size interconnected dies and substrate or leadframe structure; and

an encapsulant formed over a portion of the substrate or leadframe structure and the stacked same-size interconnected dies.

9. The semiconductor package of claim 8 , further including a conductive lid disposed over a surface of the substrate or leadframe structure.

10. The semiconductor package of claim 9 , wherein the first die of the plurality of stacked same-size interconnected dies is attached to the conductive lid using a die attach adhesive material.

11. The semiconductor package of claim 8 , wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

12. The semiconductor package of claim 8 wherein the plurality of conductive THVs surround the periphery of each die.

13. A method of manufacturing a semiconductor package, comprising:

providing a substrate or leadframe structure;

providing a plurality of stacked same-size interconnected dies disposed over the substrate or leadframe structure, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

forming a plurality of bond pads on the top surface of each of the stacked same-size interconnected dies;

forming a plurality of conductive traces on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs; and

depositing an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of dies.

14. The method of manufacture of claim 13 , wherein the first die of the plurality of stacked same-size interconnected dies is wire-bonded to the substrate or leadframe structure.

15. The method of manufacture of claim 14 , further including forming a wire between the substrate or leadframe structure and a terminal land.

16. The method of manufacture of claim 13 , further including disposing a conductive lid over a surface of the substrate or leadframe structure.

17. The method of manufacture of claim 16 , further including attaching the first die of the plurality of stacked same-size interconnected dies to the conductive lid using a die attach adhesive material.

18. The method of manufacture of claim 13 , wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

19. The method of manufacture of claim 13 , wherein each of the plurality of stacked same-size interconnected dies has a substantially similar dimensional footprint.

20. The method of claim 13 wherein the plurality of conductive THVs surround the periphery of each die.

21. A method of manufacturing a semiconductor package, comprising:

providing a substrate or leadframe structure having an integrated cavity;

providing a plurality of stacked same-size interconnected dies disposed within the integrated cavity, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

forming a plurality of bond pads on the top surface of each of the stacked same-size interconnected dies;

forming a plurality of conductive traces on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs;

forming a bond wire between the second die of the stacked same-size interconnected dies and substrate or leadframe structure; and

depositing an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of dies.

22. The method of manufacture of claim 21 , further including disposing a conductive lid over a surface of the substrate or leadframe structure.

23. The method of manufacture of claim 22 , further including attaching the first die of the plurality of interconnected dies to the conductive lid using a die attach adhesive material.

24. The method of manufacture of claim 21 , wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

25. The method of claim 21 wherein the plurality of conductive THVs surround the periphery of each die.

Assignments (6)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0328 Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064838/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0328 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2007
From: DO, BYUNG TAI; KUAN, HEAP HOE; CHOW, SENG GUAN
To: STATS CHIPPAC, LTD.
Reel/Frame 019482/0165 →