Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region
View Patent ↗A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.
1. A memory device, comprising:
a plurality of memory cells, each memory cell comprised of a stack formed over a substrate, the stack having a gate oxide layer and an overlying layer that acts as a tunneling barrier, the stack having at least one undercut region formed under the overlying layer and is adjacent to the gate oxide layer; and
at least one charge storage element formed in the at least one undercut region, the overlying layer comprising at least one of a P+ polycrystalline silicon or a P-type metal that minimizes a number of electrons tunneling from the overlying layer to the at least one charge storage element, which is in at least one memory cell of the plurality of memory cells, during a Fowler-Nordheim (FN) erase operation to erase the at least one charge storage element, wherein each of the at least one charge storage element consists of a tunnel oxide layer formed over the substrate in the undercut region, a silicon rich nitride layer formed over the tunnel oxide layer and a layer of polysilicon.
2. The memory device of claim 1 , further comprising:
silicon oxide filler formed in the space between adjacent stacks; and
a plurality of word lines formed over the silicon oxide filler and the stacks, each of the word lines is respectively associated with each of the memory cells.
3. The memory device of claim 1 , the overlying layer comprises P+ polycrystalline silicon.
4. The memory device of claim 1 , the overlying layer comprises a P-type metal.
5. The memory device of claim 1 , the overlying layer comprises a high-K material.
6. The memory device of claim 1 , the overlying layer comprises P+ polycrystalline silicon and a high-K material.
7. The memory device of claim 6 , the high-K material comprising a material having a dielectric constant greater than 3.9.
8. The memory device of claim 1 , the memory device is a non-volatile memory device.
9. An electronic device comprising the memory device of claim 1 .
10. The electronic device of claim 9 , wherein the electronic device comprises at least one of a computer, a laptop computer, network equipment, a media player, a media recorder, a television, a smart card, a phone, a cellular phone, a smart phone, an electronic organizer, a personal digital assistant, a portable email reader, a digital camera, an electronic game, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), a Hardware Security Module (HSM), set-top boxes, a digital video recorder, a gaming console, a navigation system, a secure memory device with computational capabilities, a device with at least one tamper-resistant chip, an electronic device associated with industrial control systems, or an embedded computer in a machine, or a combination thereof, wherein the machine comprises one of an airplane, a copier, a motor vehicle, or a microwave oven.
11. A method for fabricating a memory device, comprising:
forming at least one memory cell in the memory device;
creating at least one charge storage element in at least one undercut region within the at least one memory cell, wherein each of the at least one charge storage element consists of a tunnel oxide layer formed over the substrate in the undercut region, a silicon rich nitride layer formed over the tunnel oxide layer and a layer of polysilicon; and
forming a tunneling barrier on top of the at least one memory cell, the tunneling barrier is at least one of a high work function material or a high-K material, or a combination thereof, the high function work material comprising one of a P+ polycrystalline silicon or a P-type metal, which minimizes a number of electrons tunneling from a gate electrode of the at least one memory cell to the at least one charge storage element during a Fowler-Nordheim (FN) erase operation to erase the at least one charge storage element.
12. The method of claim 11 , the forming the tunneling barrier on top of the at least one memory cell further comprises forming a layer comprising the P+ polycrystalline silicon on top of the at least one memory cell.
13. The method of claim 12 , the forming a tunneling barrier on top of the at least one memory cell further comprises forming a layer comprising the high-K material on top of the at least one memory cell underneath the layer comprising the P+ polycrystalline silicon.
14. The method of claim 11 , the forming the tunneling barrier on top of the at least one memory cell further comprises forming a layer comprising the P-type metal on top of the gate silicon oxide.
15. The method of claim 11 , further comprising:
creating at least one undercut region within the at least one memory cell;
growing at least one tunnel oxide layer in the at least one undercut region;
depositing a layer of silicon nitride over the at least one tunnel oxide layer;
forming sidewall spacers within the at least one memory cell; and
filling a remainder of the undercut region.
16. The method of claim 11 , the creating of at least one charge storage element in at least one undercut region within the at least one memory cell further comprises selectively etching a gate silicon oxide layer of the at least one memory cell to create the at least one undercut region.
17. The method of claim 11 , further comprising:
stripping at least one of a top layer or a top portion of an oxide layer, or combination thereof from the memory device;
at least one of:
regrowing the top portion of the oxide layer, or
depositing the high-K material to form a high-K layer, the high-K layer comprises at least part of the tunneling barrier formed on top of the at least one memory cell.
18. The method of claim 17 , further comprising:
depositing a new top layer, the new top layer comprising one of the P+ polycrystalline silicon or the p-type metal, and comprises at least part of the tunneling barrier formed on top of the at least one memory cell.
19. A system that facilitates fabrication of a memory array in a memory, comprising:
a storage element formation component that forms at least one charge storage element in at least one undercut region of at least one memory cell stack, the at least one memory cell stack associated with the memory array in the memory; and
a tunneling barrier formation component that forms a tunneling barrier on top of the at least one memory cell stack, the tunneling barrier is at least one of a layer of a high work function material, comprising one of a P+ polycrystalline silicon or a P-type metal, or a layer of a high-K material, or a combination thereof, that optimally reduces a number of electrons tunneling from the tunneling barrier layer to the at least one charge storage element, which is in at least one memory cell of the memory array, during a Fowler-Nordheim (FN) erase operation to erase the at least one charge storage element, wherein each of the at least one charge storage element consists of a tunnel oxide layer formed over the substrate in the undercut region, a silicon rich nitride layer formed over the tunnel oxide layer and a layer of polysilicon.
20. The system of claim 19 , further comprising:
an undercut formation component that forms at least two undercut regions in each of multiple stacks of silicon oxide;
a bit line formation component that forms bits lines between the stacks, each bit line is associated with a respective memory cell;
a spacer formation component that forms a sidewall spacer around each wall of each stack and fills in space between the stacks; and
a word line formation component that forms word lines for the memory array between the stacks, each word line is respectively associated with a memory cell.
21. The system of claim 19 , the tunneling baffler formation component strips a gate electrode layer or a top portion of an oxide layer, or a combination thereof, from a top of each memory cell stack, and deposits a new gate electrode layer comprising the high work function material or the layer of high-K material, or a combination thereof, on top of each memory cell stack to form the tunneling barrier, wherein the stripped gate electrode layer comprises one of a P+ polycrystalline silicon, p-type metal, or N+-type polysilicon.