IP Library Granted Patent US 7,642,128
Granted Patent B1
US 7,642,128 · App. 12/333,977 · Granted Jan 5, 2010

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

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Quick Facts
Patent No.
US 7,642,128
App. No.
12/333,977
Granted
Jan 5, 2010
Kind
B1
Abstract

A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Claims (49)

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

depositing an interface layer over the temporary carrier;

forming a first conductive layer over the interface layer, the first conductive layer having a first area electrically isolated from a second area of the first conductive layer;

forming a conductive pillar over the first area of the first conductive layer;

mounting a semiconductor die or component to the second area of the first conductive layer;

depositing an encapsulant over the semiconductor die and around the conductive pillar;

forming a first interconnect structure over the encapsulant, the first interconnect structure being electrically connected to the conductive pillar;

removing the temporary carrier and interface layer;

removing a portion of the first area of the first conductive layer; and

forming a second interconnect structure over a remaining portion of the first conductive layer.

2. The method of claim 1 , wherein the first conductive layer includes a plurality of conductive layers.

3. The method of claim 1 , further including forming a second conductive layer over the first conductive layer.

4. The method of claim 3 , wherein the second conductive layer includes a plurality of conductive layers.

5. The method of claim 1 , wherein forming the first interconnect structure includes:

forming a first insulating layer over the encapsulant;

forming a second conductive layer over the first insulating layer, the second conductive layer being electrically connected to the conductive pillars; and

forming a second insulating layer over the second conductive layer.

6. The method of claim 1 , wherein the remaining portion of the first conductive layer includes an interconnect line and under bump metallization pad.

7. The method of claim 1 , further including forming a solder bump over the conductive pillar.

8. A method of making a semiconductor device, comprising:

providing a carrier;

forming a first conductive layer over the carrier, the first conductive layer having a first area electrically isolated from a second area of the first conductive layer;

forming a conductive pillar over the first area of the first conductive layer;

mounting a semiconductor die or component to the second area of the first conductive layer;

depositing a first encapsulant over the semiconductor die and around the conductive pillar;

forming a first interconnect structure over the first encapsulant, the first interconnect structure being electrically connected to the conductive pillar;

removing the carrier; and

removing a portion of the first area of the first conductive layer.

9. The method of claim 8 , further including forming a second interconnect structure over a remaining portion of the first conductive layer.

10. The method of claim 9 , wherein the remaining portion of the first conductive layer includes an interconnect line and under bump metallization pad.

11. The method of claim 8 , wherein the first conductive layer includes a plurality of conductive layers.

12. The method of claim 8 , further including forming a second conductive layer over the first conductive layer.

13. The method of claim 12 , wherein the second conductive layer includes a plurality of conductive layers.

14. The method of claim 8 , further including forming a solder bump over the conductive pillar.

15. The method of claim 8 , further including forming a second encapsulant over the first encapsulant.

16. A method of making a semiconductor device, comprising:

providing a carrier;

forming a conductive pillar over the carrier;

mounting a semiconductor die or component to the carrier;

depositing a first encapsulant over the semiconductor die and around the conductive pillar;

forming a first interconnect structure over the first encapsulant, the first interconnect structure being electrically connected to the conductive pillar; and

removing the carrier.

17. The method of claim 16 , further including:

forming a first conductive layer over the carrier, the first conductive layer having a first area electrically isolated from a second area of the first conductive layer; and

removing a portion of the first area of the first conductive layer after removing the carrier.

18. The method of claim 17 , further including forming a second interconnect structure over a remaining portion of the first conductive layer.

19. The method of claim 16 , further including forming a solder bump over the conductive pillar.

20. The method of claim 16 , further including forming a second encapsulant over the first encapsulant.

Assignments (6)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0328 Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064838/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0328 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: LIN, YAOJIAN; BAO, XUSHENG; CHEN, KANG; FANG, JIANMIN
To: STATS CHIPPAC, LTD.
Reel/Frame 021972/0863 →