Pipelined data relocation and improved chip architectures
View Patent ↗The present invention presents methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural examples are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
1. A memory system, comprising:
a controller; and
a memory, including
a non-volatile data storage section;
a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and
a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller,
wherein a second data set transferred from the second data register can be operated upon in the controller concurrently with transferring a first data set between said first data register and the non-volatile data storage section, and
wherein the controller includes error correction circuitry and the controller can perform error correction operations upon the second data set concurrently with transferring the first data set between the first data register and the non-volatile data storage section.
2. A memory system, comprising:
a controller; and
a memory, including
a non-volatile data storage section;
a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and
a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller,
wherein a second data set transferred from the second data register can be operated upon in the controller concurrently with transferring a first data set between said first data register and the non-volatile data storage section, and
wherein the controller can perform data verification operations upon the second data set concurrently with transferring the first data set between the first data register and the non-volatile data storage section.
3. A memory system, comprising:
a controller; and
a memory, including
a non-volatile data storage section;
a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and
a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller,
wherein said controller includes a plurality of data buffers and wherein the controller can perform a data checking operation on the contents of a first of said data buffers concurrently with transferring data between another of said data buffers and said memory.
4. The memory system of claim 3 , wherein said data checking operation is an error detection and correction operation.
5. The memory system of claim 3 , wherein said data checking operation is program-verify operation.
6. A method of operating a memory system comprising a controller and a memory including first and second data registers and a non-volatile data storage section, the method comprising:
loading first data into a first of said data registers from either the data storage section or the controller;
loading second data into the second of said data registers from either the data storage section or the controller; and
swapping on the memory the contents of the first and second data registers in response to a command from the controller,
wherein the first data is loaded from the controller and the second data is loaded from the data storage section, further comprising, subsequent to said swapping:
transferring the second data from first data register to the controller; and
checking/correcting the second data by the controller.
7. The method of claim 6 , wherein said checking/correcting the second data comprises:
determining the quality of the second data; and
in response to said determining the quality of the second data, correcting the second data,
the method further comprising:
transferring back the corrected second data from the controller to the first data register; and
programming the first data from the second data register to the data storage section, wherein said checking/correcting the second data and the transferring the second data to and back from the controller is performed concurrently with said programming first data.