Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects
View Patent ↗A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset. In one embodiment, the bias conditions for the string during each individual erase are selected so that every memory cell of the set will experience similar capacitive coupling effects from neighboring transistors.
1. A method of erasing non-volatile storage, comprising:
receiving an erase request including a string of non-volatile storage elements designated for erase;
erasing a first subset of non-volatile storage elements in said string of non-volatile storage elements by applying a first erase voltage pulse to said string while enforcing a first voltage condition on said first subset and a second voltage condition on a second subset of non-volatile storage elements in said string, wherein non-volatile storage elements in said second subset are adjacent to non-volatile storage elements in of said first subset; and
erasing said second subset by applying a second erase voltage pulse to said string while enforcing said first voltage condition on said second subset and said second voltage condition on said first subset, said first voltage condition is different from said second voltage condition.
2. The method of claim 1 , wherein:
enforcing said first voltage condition on said first subset comprises applying 0 volts to each word line connected to said first subset;
enforcing said second voltage condition on said second subset comprises electrically floating each word line connected to said second subset; and
said method further comprises electrically floating a first select gate line and a second select gate line for said string while applying said first erase voltage pulse.
3. The method of claim 2 , wherein:
enforcing said first voltage condition on said second subset comprises applying 0 volts to each word line connected to said second subset;
enforcing said second voltage condition on of said first subset comprises electrically floating each word line connected to said first subset; and
said method further comprises electrically floating said first select gate line and said second select gate line for said string while applying said second erase voltage pulse.
4. The method of claim 1 , wherein:
said string is a NAND string of multi-state flash memory devices.
5. A method of erasing non-volatile storage, comprising:
receiving an erase request including a string of non-volatile storage elements designated for erase, said string includes a plurality of transistors, said transistors include non-volatile storage elements of said string and first and second select gates for said string;
erasing a first subset of non-volatile storage elements in said string by applying a first erase voltage pulse to said string while enforcing a first voltage condition on said first subset, enforcing said first voltage condition on a first transistor adjacent to each non-volatile storage element in said first subset, and enforcing a second voltage condition on a second transistor adjacent to each non-volatile storage element in a second subset, said first voltage condition is different from said second voltage condition; and
erasing said second subset of non-volatile storage elements in said string by applying a second erase voltage pulse to said string while enforcing said first voltage condition on said second subset, enforcing said first voltage condition on a first transistor adjacent to each non-volatile storage element in said second subset, and enforcing said second voltage condition on a second transistor adjacent to each non-volatile storage element in said first subset.
6. The method of claim 5 , wherein:
said first transistors adjacent to each non-volatile storage element in said first subset are other non-volatile storage elements of said first subset;
said second transistors adjacent to each non-volatile storage element in said first subset include non-volatile storage elements in said second subset and said first select gate for said string;
said first transistors adjacent to each non-volatile storage element in said second subset are other non-volatile storage elements of said second subset; and
said second transistors adjacent to each non-volatile storage element in said second subset include non-volatile storage elements in said first subset and said second select gate for said string.
7. The method of claim 5 , wherein:
enforcing said first voltage condition on each non-volatile storage element in said first subset comprises applying 0 volts to a gate of said non-volatile storage elements in said first subset;
enforcing said first voltage condition on each non-volatile storage element in said second subset comprises applying 0 volts to a gate of said non-volatile storage elements in said first subset;
enforcing said second voltage condition on a second transistor adjacent to each non-volatile storage element in said first subset comprises allowing a gate of said second transistors to float; and
enforcing said second voltage condition on a second transistor adjacent to each non-volatile storage element in said second subset comprises allowing a gate of said second transistors to float.
8. The method of claim 5 , wherein:
said string is a NAND string of flash memory devices.
9. A method of erasing non-volatile storage, comprising:
receiving an erase request including a string of non-volatile storage elements designated for erase;
erasing a first subset of non-volatile storage elements in said string by applying a first erase voltage pulse to said string while enforcing a first voltage condition on said first subset and a second voltage condition on a second subset of non-volatile storage elements in said string, wherein said first subset includes a first non-volatile storage element adjacent to a first select gate for said string, said first non-volatile storage element is coupled to a word line N, said first subset includes non-volatile storage elements in said string that are coupled to word lines in a series defined by {N; N+2; N+4}, said second subset includes non-volatile storage elements in said string that are coupled to word lines in a series defined by {N+1; N+3; N+5}; and
erasing said second subset by applying a second erase voltage pulse to said string while enforcing said first voltage condition on said second subset and said second voltage condition on said first subset, said first voltage condition is different from said second voltage condition.
10. A method according to claim 9 , wherein:
enforcing said first voltage condition on said first subset comprises applying 0 volts to word lines coupled to said first subset;
enforcing said second voltage condition on said second subset comprises electrically floating word lines coupled to said second subset; and
said method further comprises electrically floating a first select gate line and a second select gate line for said string while applying said first erase voltage pulse.
11. A method according to claim 10 , wherein:
enforcing said first voltage condition on said second subset comprises applying 0 volts to word lines coupled to said second subset;
enforcing said second voltage condition on said first subset comprises electrically floating word lines coupled to said first subset; and
said method further comprises electrically floating said first select gate line and said second select gate line for said string while applying said second erase voltage pulse.
12. A method according to claim 9 , wherein:
said string of non-volatile storage elements is a NAND string.
13. A method of erasing non-volatile storage, comprising:
receiving an erase request including a string of non-volatile storage elements designated for erase;
erasing a first subset of non-volatile storage elements in said string by applying a first erase voltage pulse to said string while enforcing a first voltage condition on said first subset and a second voltage condition on a second subset of non-volatile storage elements in said string, wherein said first subset includes a first non-volatile storage element adjacent to a first select gate for said string, said first non-volatile storage element coupled to a word line N, said first subset includes non-volatile storage elements of said string that are coupled to word lines in a series defined by {N; N+1; N+4; N+5}, said second subset includes non-volatile storage elements of said string that are coupled to word lines in a series defined by {N+2; N+3; N+6; N+7}; and
erasing said second subset by applying a second erase voltage pulse to said string while enforcing said first voltage condition on said second subset and said second voltage condition on said first subset, said first voltage condition is different from said second voltage condition.
14. A method according to claim 13 , wherein:
enforcing said first voltage condition on said first subset comprises applying 0 volts to word lines coupled to said first subset;
enforcing said second voltage condition on said second subset comprises electrically floating word lines coupled to said second subset; and
said method further comprises electrically floating a first select gate line for said string while applying said first erase voltage pulse.
15. A method according to claim 14 , wherein:
enforcing said first voltage condition on said second subset comprises applying 0 volts to word lines coupled to said second subset;
enforcing said second voltage condition on said first subset comprises electrically floating word lines coupled said first subset; and
said method further comprises electrically floating a second select gate line for said string while applying said second erase voltage pulse.
16. A method according to claim 13 , wherein:
said string of non-volatile storage elements is a NAND string.