Semiconductor memory with improved memory block switching

1. A method for operating a non-volatile storage system, comprising:

setting a first group of non-volatile storage elements into an active state, said setting a first group of non-volatile storage elements into said active state includes biasing a plurality of first control lines to one or more unselected voltages, each first control line is coupled to a subset of said first group of non-volatile storage elements;

setting a second group of non-volatile storage elements into an inactive state, each non-volatile storage element of a subset of said second group of non-volatile storage elements is coupled to one of a plurality of second control lines; and

transitioning said second group of non-volatile storage elements from said inactive state to said active state, said transitioning includes sharing charge between said plurality of first control lines and said plurality of second control lines.

2. A method according to claim 1 , further comprising:

floating said plurality of second control lines when said second group of non-volatile storage elements is in said inactive state;

reading data from said second group of non-volatile storage elements when said second group of non-volatile storage elements is in said active state; and

outputting said data read to a host.

3. A method according to claim 1 , wherein:

said active state is a read state.

4. A method according to claim 1 , wherein:

said transitioning includes controlling a charge transfer circuit, said charge transfer circuit is coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a switch, said transitioning includes turning off said switch during charge sharing to prevent the electrical coupling of said one or more unselected voltages to said plurality of first control lines.

5. A method according to claim 1 , wherein:

said first group of non-volatile storage elements is part of a first memory block;

said second group of non-volatile storage elements is part of a second memory block, said first memory block and said second memory block are in a common memory bay;

said plurality of first control lines comprise a plurality of bit lines; and

said non-volatile storage elements comprise two-terminal non-volatile memory cells.

6. A method according to claim 1 , wherein:

said transitioning includes latching a first block enable signal, said first block enable signal is an input to a charge transfer circuit, said charge transfer circuit is coupled to said plurality of first control lines and to said plurality of second control lines, said first block enable signal controls the electrical coupling of said plurality of first control lines to said plurality of second control lines during said transitioning; and

said transitioning includes changing said first group of non-volatile storage elements from said active state to said inactive state.

7. A method according to claim 1 , wherein:

said transitioning includes latching a first block enable signal, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node; and

said transitioning includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said transitioning includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.

8. A method according to claim 1 , wherein:

said active state is a write state.

9. A method according to claim 8 , wherein:

said plurality of first control lines are biased to one or more unselected voltages in a SET mode.

10. A method according to claim 8 , wherein:

said plurality of first control lines are biased to one or more unselected voltages in a RESET mode.

11. A method for operating a non-volatile storage system, comprising:

decoding a read command from a host;

identifying a set of memory blocks that contain requested data to be read;

setting a first memory block into a read state, said first memory block comprises a first plurality of bit lines, said first plurality of bit lines are biased to one or more unselected bit line voltages when said first memory block is in said read state;

setting a second memory block into an inactive state, said second memory block comprises a second plurality of bit lines, said second plurality of bit lines are floated when said second memory block is in said inactive state;

reading data from said first memory block;

transitioning said first memory block into said inactive state and said second memory block into said read state, said transitioning includes sharing charge between said first memory block and said second memory block;

reading data from said second memory block; and

outputting the data read to said host.

12. A method for operating a non-volatile storage system, comprising:

decoding a read command from a host;

identifying a set of memory blocks that contain requested data to be read;

setting a first memory block into a read state, said first memory block comprises a plurality of first control lines;

setting a second memory block into an inactive state;

reading data from said first memory block;

transitioning said first memory block into said inactive state and said second memory block into said read state, said transitioning includes sharing charge between said first memory block and said second memory block, said transitioning includes controlling a charge transfer circuit, said charge transfer circuit is coupled to both said first memory block and said second memory block, said charge transfer circuit comprises a switch, said transitioning includes turning off said switch during charge sharing to prevent the electrical coupling of one or more unselected voltages to said plurality of first control lines, said transitioning includes latching a first block enable signal, said first block enable signal is an input to said charge transfer circuit and controls charge sharing between said first memory block and said second memory block during said transitioning;

reading data from said second memory block; and

outputting the data read to said host.

13. A method for operating a non-volatile storage system, comprising:

biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements, said first plurality of non-volatile storage elements are part of a first memory block;

floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements, said second plurality of non-volatile storage elements are part of a second memory block; and

setting up read conditions for said second plurality of non-volatile storage elements, said setting up read conditions includes sharing charge between said plurality of first control lines and said plurality of second control lines, said plurality of first control lines comprise a plurality of unselected bit lines, each unselected bit line is biased to one or more unselected bit line voltages prior to said setting up read conditions.

14. A method according to claim 13 , wherein:

said setting up read conditions includes controlling a charge transfer circuit, said charge transfer circuit includes a first switch and a second switch, said first switch electrically couples said plurality of first control lines to an intermediate node, said second switch electrically couples said intermediate node to said one or more unselected bit line voltages, said controlling the charge transfer circuit includes turning off said second switch during charge sharing to prevent the electrical coupling of said one or more unselected bit line voltages to said intermediate node, said controlling the charge transfer circuit includes latching a first enable signal, said first enable signal controls said first switch during said setting up read conditions.

15. A method for operating a non-volatile storage system, comprising:

biasing a plurality of first control lines, each first control line is coupled to a respective subset of a first plurality of non-volatile storage elements, said non-volatile storage elements comprise two-terminal non-volatile memory cells;

floating a plurality of second control lines, each second control line is coupled to a respective subset of a second plurality of non-volatile storage elements; and

setting up read conditions for said second plurality of non-volatile storage elements, said setting up read conditions includes sharing charge between said plurality of first control lines and said plurality of second control lines, said setting up read conditions includes latching a first block enable signal, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node, said setting up read conditions includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said setting up read conditions includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.

16. A non-volatile storage system, comprising:

non-volatile storage elements including a first set of said non-volatile storage elements and a second set of said non-volatile storage elements;

a plurality of first control lines, each first control line is coupled to a respective subset of said first set of non-volatile storage elements;

a plurality of second control lines, each second control line is coupled to a respective subset of said second set of non-volatile storage elements; and

a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a first switch, said first switch controls charge sharing between said plurality of first control lines and said plurality of second control lines while setting up read conditions for said second set of non-volatile storage elements, said plurality of first control lines comprise a plurality of unselected bit lines, said plurality of unselected bit lines are biased to one or more unselected bit line voltages prior to said setting up read conditions.

17. The non-volatile storage system of claim 16 , further comprising:

a latch, said first set of non-volatile storage elements is part of a first memory block, said latch latches a first block enable signal associated with said first memory block during said setting up read conditions, said first block enable signal controls said first switch.

18. A non-volatile storage system, comprising;

non-volatile storage elements including a first set of said non-volatile storage elements and a second set of said non-volatile storage elements;

a plurality of first control lines, each first control line is coupled to a respective subset of said first set of non-volatile storage elements, said plurality of first control lines comprise a plurality of unselected word lines;

a plurality of second control lines, each second control line is coupled to a respective subset of said second set of non-volatile storage elements; and

a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit comprises a first switch, said first switch controls charge sharing between said plurality of first control lines and said plurality of second control lines while setting up read conditions for said second set of non-volatile storage elements, said plurality of second control lines are not biased to any voltage prior to said setting up read conditions, said setting up read conditions includes latching a first block enable signal, said first block enable signal controls said first switch, said first switch controls coupling of said plurality of first control lines to an intermediate node, said setting up read conditions includes generating a second block enable signal, said second block enable signal controls a second switch, said second switch controls coupling of said plurality of second control lines to said intermediate node, said setting up read conditions includes said first block enable signal turning on said first switch at the same time said second block enable signal turns on said second switch.

19. A non-volatile storage system, comprising:

a first memory block comprising a plurality of first control lines, said first memory block set into a read state;

a second memory block comprising a plurality of second control lines, said second memory block set into an inactive state;

a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit controls charge sharing between said plurality of first control lines and said plurality of second control lines during a transitioning of said second memory block from said inactive state into said read state; and

a latch, said latch latches a first block enable signal associated with said first memory block during said transitioning, said first block enable signal controls the electrical coupling of said plurality of first control lines to said plurality of second control lines, said plurality of second control lines comprise a plurality of unselected bit lines.

20. A non-volatile storage system, comprising:

a first memory block comprising a plurality of first control lines, said first memory block set into a read state;

a second memory block comprising a plurality of second control lines, said second memory block set into an inactive state;

a charge transfer circuit coupled to both said plurality of first control lines and said plurality of second control lines, said charge transfer circuit controls charge sharing between said plurality of first control lines and said plurality of second control lines during a transitioning of said second memory block from said inactive state into said read state;

a latch, said latch latches a first block enable signal during said transitioning, said first block enable signal controls a first switch, said first switch controls the electrical coupling of said plurality of first control lines to an intermediate node; and

a second block enable signal, said second block enable signal controls a second switch, said second switch controls the electrical coupling of said plurality of second control lines to said intermediate node, said first block enable signal turns on said first switch at the same time said second block enable signal turns on said second switch.