IP Library Granted Patent US 8,847,200
Granted Patent B2
US 8,847,200 · App. 13/182,960 · Granted Sep 30, 2014

Memory cell comprising a carbon nanotube fabric element and a steering element

Inventors: Scott Brad Herner (San Jose, CA); Roy E. Scheuerlein (Cupertino, CA)
Assignee: SanDisk 3D LLC
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Quick Facts
Patent No.
US 8,847,200
App. No.
13/182,960
Granted
Sep 30, 2014
Kind
B2
Abstract

A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.

Claims (26)

1. A memory cell comprising:

a steering element comprising a vertically-oriented p-i-n junction; and

a carbon nanotube fabric;

wherein the steering element and the carbon nanotube fabric are arranged electrically in series, and

wherein the entire memory cell is formed above a substrate.

2. The memory cell of claim 1 , wherein the steering element and the carbon nanotube fabric are disposed between a first conductor and a second conductor.

3. The memory cell of claim 1 , wherein the carbon nanotube fabric is disposed between and permanently in contact with first and second metal or metallic elements.

4. The memory cell of claim 3 , wherein the first or second metal or metallic elements comprise titanium nitride, tantalum nitride, or tungsten.

5. The memory cell of claim 3 , wherein the first metal or metallic element is below and permanently in contact with the carbon nanotube fabric and the second metal or metallic element is above and permanently in contact with the carbon nanotube fabric.

6. The memory cell of claim 1 , further comprising a silicide layer adjacent the steering element.

7. The memory cell of claim 6 wherein the silicide layer is titanium silicide or cobalt silicide.

8. The memory cell of claim 1 , wherein the steering element comprises a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region.

9. The memory cell of claim 8 , wherein the middle intrinsic or lightly doped region comprises a layer of silicon-germanium.

10. The memory cell of claim 9 , wherein the layer of silicon-germanium is at least 10 at% germanium.

11. A monolithic three dimensional memory array comprising:

(a) a first memory level comprising a plurality of memory cells, wherein each memory cell comprises a steering element and a carbon nanotube fabric element arranged electrically in series between a bottom conductor and a top conductor; and

(b) a second memory level monolithically formed above the first memory level.

12. The monolithic three dimensional memory array of claim 11 , wherein each of the steering elements comprises a junction diode.

13. The monolithic three dimensional memory array of claim 11 , wherein each of the steering elements comprises a vertically oriented p-i-n diode.

14. The monolithic three dimensional memory array of claim 13 , wherein each of the carbon nanotube fabric elements is disposed between one of the bottom conductors and one of the p-i-n diodes.

15. The monolithic three dimensional memory array of claim 13 , wherein each of the p-i-n diodes comprises a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region.

16. The monolithic three dimensional memory array of claim 13 , wherein each of the p-i-n diodes comprises a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region.

17. The monolithic three dimensional memory array of claim 11 , wherein, in each memory cell, the top conductor is above the bottom conductor.

18. The monolithic three dimensional memory array of claim 11 , wherein each memory cell further comprises a silicide layer disposed adjacent the steering element of the memory cell.

19. The monolithic three dimensional memory array of claim 18 , wherein the silicide layer comprises titanium silicide or cobalt silicide.

20. The monolithic three dimensional memory array of claim 11 , wherein each of the top conductors comprises a bottom layer, wherein the bottom layer comprises titanium or cobalt.

Assignments (6)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0850 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
Continuity (2)
Continuation 11692148 · Mar 27, 2007
Related Publication 20110266514A1 · Nov 3, 2011