INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.
1 . A method of manufacture of an integrated circuit packaging system comprising:
providing a substrate having a substrate first side and a substrate second side opposite the substrate first side;
attaching a base integrated circuit to the substrate first side;
attaching a mountable integrated circuit to the substrate second side;
attaching a via base to the substrate second side adjacent the mountable integrated circuit;
forming a device encapsulation surrounding the via base and the mountable integrated circuit; and
forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.
2 . The method as claimed in claim 1 wherein forming the via extension includes forming the via extension having a tapered shape with the width of end of the via extension exposed from the device encapsulation greater than the width of the end of the via extension attached to the via base.
3 . The method as claimed in claim 1 further comprising forming a circuit encapsulation on the substrate first side and surrounding the base integrated circuit.
4 . The method as claimed in claim 1 wherein forming the device encapsulation includes filling the space between the mountable integrated circuit and the substrate second side with the device encapsulation.
5 . The method as claimed in claim 1 further comprising attaching a conductive cover to the substrate first side and over the base integrated circuit.
6 . A method of manufacture of an integrated circuit packaging system comprising:
providing a substrate having a substrate first side and a substrate second side opposite the substrate first side;
attaching a base integrated circuit to the substrate first side;
attaching a mountable integrated circuit to the substrate second side;
attaching a via base to the substrate second side adjacent the mountable integrated circuit;
forming a device encapsulation, having an encapsulation outer side facing away from the substrate second side, on the substrate second side surrounding the via base and the mountable integrated circuit; and
forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation along the encapsulation outer side.
7 . The method as claimed in claim 6 wherein forming the via extension includes forming the via extension exposed from the device encapsulation coplanar with the encapsulation outer side.
8 . The method as claimed in claim 6 further comprising attaching a further base integrated circuit to the substrate first side and adjacent to the base integrated circuit.
9 . The method as claimed in claim 6 further comprising attaching an external interconnect to the portion of the via extension exposed from the device encapsulation.
10 . The method as claimed in claim 6 wherein attaching the mountable integrated circuit includes attaching a flip chip.
11 . An integrated circuit packaging system comprising:
a substrate having a substrate first side and a substrate second side opposite the substrate first side;
a base integrated circuit attached to the substrate first side;
a mountable integrated circuit attached to the substrate second side;
a via base attached to the substrate second side adjacent the mountable integrated circuit;
a device encapsulation surrounding the via base and the mountable integrated circuit; and
a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.
12 . The system as claimed in claim 11 wherein the via extension has a tapered shape with the width of end of the via extension exposed from the device encapsulation greater than the width of the end of the via extension attached to the via base.
13 . The system as claimed in claim 11 further comprising a circuit encapsulation on the substrate first side and surrounding the base integrated circuit.
14 . The system as claimed in claim 11 wherein the device encapsulation fills the space between the mountable integrated circuit and the substrate second side.
15 . The system as claimed in claim 11 further comprising a conductive cover attached to the substrate first side and over the base integrated circuit.
16 . The system as claimed in claim 11 wherein:
the device encapsulation includes an encapsulation outer side facing away from the substrate second side; and
the via extension is exposed from the device encapsulation along the encapsulation outer side.
17 . The system as claimed in claim 16 wherein the portion of the via extension exposed from the device encapsulation is coplanar with the encapsulation outer side.
18 . The system as claimed in claim 16 further comprising a further base integrated circuit attached to the substrate first side adjacent to the base integrated circuit.
19 . The system as claimed in claim 16 further comprising an external interconnect attached to the portion of the via extension exposed from the device encapsulation.
20 . The system as claimed in claim 16 wherein the mountable integrated circuit includes a flip chip.