IP Library Granted Patent US 9,576,873
Granted Patent B2
US 9,576,873 · App. 13/325,881 · Granted Feb 21, 2017

Integrated circuit packaging system with routable trace and method of manufacture thereof

Inventors: Byung Tai Do (Singapore, SG); Arnel Senosa Trasporto (Singapore, SG); Linda Pei Ee Chua (Singapore, SG)
Assignee: STATS ChipPAC Pte. Ltd.
H01L23/3128H01L21/4832H01L21/563H01L21/565H01L23/49517H01L23/49548H01L23/49582H01L25/105H01L24/48H01L24/73H01L2224/16145H01L2224/32145H01L2224/32245H01L2224/48145H01L2224/48247H01L2224/73265H01L2225/1029H01L2225/1058H01L2924/10253H01L2924/12042H01L2924/15321
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Quick Facts
Patent No.
US 9,576,873
App. No.
13/325,881
Granted
Feb 21, 2017
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.

Claims (43)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a lead having a top lead side opposite a bottom lead side;

forming routable traces directly on the top lead side, the routable traces having a top plate mounted thereon, and a portion of the routable traces completely covering a side of the top plate facing the routable traces;

mounting an integrated circuit partially over the routable traces;

forming an encapsulation over and around the routable traces and the integrated circuit;

forming a hole through the encapsulation to the top plate; and

forming a protective coat having a top coat side directly on a side of the routable traces facing opposite of the top plate and the protective coat directly on the encapsulation and a non-horizontal side of the lead.

2. The method as claimed in claim 1 further comprising filling a conductive fill in the hole, the conductive fill having a lower volume than the hole of the encapsulation.

3. The method as claimed in claim 1 wherein forming the routable traces includes:

providing a leadframe;

forming the routable traces on the leadframe; and

forming the lead by removing a portion of the leadframe.

4. The method as claimed in claim 1 further comprising mounting a top package substrate on the encapsulation, the top package substrate electrically connected to the top plate through a conductive fill in the hole.

5. The method as claimed in claim 1 further comprising:

mounting an external interconnect under the routable traces; and

wherein:

forming the protective coat includes forming the protective coat with the external interconnect partially surrounded by the protective coat.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming routable traces on a leadframe, the routable traces include a top plate mounted thereon with a portion of the routable traces completely covering a side of the top plate facing the routable traces;

mounting an integrated circuit partially over the routable traces;

forming an encapsulation over and around the routable traces and the integrated circuit;

etching the leadframe to electrically isolate a lead having the routable traces directly on a top lead side of the lead and the top lead side opposite a bottom lead side;

forming a hole through the encapsulation to the top plate; and

forming a protective coat having a top coat side directly on a side of the routable traces facing opposite of the top plate and the protective coat directly on the encapsulation and a non-horizontal side of the lead.

7. The method as claimed in claim 6 wherein forming the hole includes lasering the encapsulation.

8. The method as claimed in claim 6 further comprising attaching an external board under the routable traces with the external board electrically connected to the routable traces.

9. The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting an integrated circuit stack having the integrated circuit.

10. The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting the integrated circuit with a die interconnect between the integrated circuit and the routable traces, the die interconnect surrounded by an attachment layer.

11. An integrated circuit packaging system comprising:

a lead having a top lead side opposite a bottom lead side;

routable traces directly on the top lead side of the lead, the routable traces having a top plate mounted thereon, and a portion of the routable traces completely covering a side of the top plate facing the routable traces;

an integrated circuit partially over the routable traces;

an encapsulation over and around the routable traces and the integrated circuit, the encapsulation having a hole through the encapsulation to the top plate; and

a protective coat having a top coat side directly on a side of the routable traces facing opposite the top plate and the protective coat directly on the encapsulation and a non-horizontal side of the lead.

12. The system as claimed in claim 11 further comprising a conductive fill in the hole, the conductive fill having a lower volume than the hole of the encapsulation.

13. The system as claimed in claim 11 wherein the lead is directly on an external plate.

14. The system as claimed in claim 11 further comprising a top package substrate on the encapsulation, the top package substrate electrically connected to the top plate through a conductive fill in the hole.

15. The system as claimed in claim 11 further comprising an external interconnect mounted under the routable traces and surrounded by the protective coat.

16. The system as claimed in claim 11 further comprising a lead electrically isolated from another of the lead, a portion of the routable traces directly on the lead.

17. The system as claimed in claim 16 wherein the encapsulation in the hole has laser ablation marks.

18. The system as claimed in claim 16 further comprising an external board attached under the routable traces and electrically connected to the routable traces.

19. The system as claimed in claim 16 wherein the integrated circuit is part of an integrated circuit stack.

20. The system as claimed in claim 16 further comprising a die interconnect between the integrated circuit and the routable traces, the die interconnect surrounded by an attachment layer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 18, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052972/0001 →
CHANGE OF NAME Recorded Jul 22, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039439/0240 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2012
From: DO, BYUNG TAI; TRASPORTO, ARNEL SENOSA; CHUA, LINDA PEI EE
To: STATS CHIPPAC LTD.
Reel/Frame 028616/0909 →
Continuity (1)
Related Publication 20130154105A1 · Jun 20, 2013