Bipolar junction transistors with reduced base-collector junction capacitance
Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.
1. A method of fabricating a bipolar junction transistor, the method comprising:
forming an isolation region surrounding a collector region in a substrate comprised of a first semiconductor material that is single crystal;
forming an intrinsic base layer on the collector region;
using a first etching process, forming a trench having a first section extending through the intrinsic base layer and a second section extending into the collector region, wherein the second section of the trench includes a plurality of sidewalls bordered by the collector region; and
etching the collector region adjacent to the second section of the trench with a second etching process that etches different crystallographic directions of the first semiconductor material of the substrate at different etch rates,
wherein a section of the collector region is laterally positioned between the sidewalls of the second section of the trench and the isolation region.
2. The method of claim 1 wherein the first etching process is a reactive ion etching process, and the first and second sections of the trench each have sidewalls aligned perpendicular to a top surface of the collector region before the second etching process.
3. The method of claim 2 wherein the second etching process is selective to a second semiconductor material comprising the intrinsic base layer such that the sidewalls of the first section of the trench are oriented perpendicular to the top surface of the collector region after the second etching process.
4. The method of claim 3 further comprising:
forming an emitter coupled with the intrinsic base layer and separated from the collector region by the intrinsic base layer.
5. The method of claim 2 wherein the sidewalls of the second section of the trench are oriented relative to a first crystallographic plane of the first semiconductor material of the substrate after the first etching process, and the sidewalls of the second section of the trench are oriented relative to a second crystallographic plane of the first semiconductor material of the substrate after the second etching process.
6. The method of claim 2 wherein the sidewalls of the second section of the trench are inclined at an angle relative to the top surface of the collector region after the second etching process.
7. The method of claim 6 wherein etching the collector region adjacent to the second section of the trench with the second etching process comprises:
partially removing the collector region such that the intrinsic base layer is undercut at the intersection of the sidewalls of the second section of the trench and the intrinsic base layer.
8. The method of claim 1 wherein etching the collector region adjacent to the second section of the trench with the second etching process comprises:
applying a solution comprising tetra-methyl-ammonium hydroxide (TMAH), potassium hydroxide (KOH), ammonium hydroxide (NH4OH), or ethylenediamine pyrocatechol (EDP) as an etchant for the second etching process.
9. The method of claim 1 further comprising:
orienting the substrate prior to the first etching process so that the first and second sections of the trench formed by the first etching process have sidewalls aligned with one of the different crystallographic directions.
10. The method of claim 1 further comprising:
after the second etching process, depositing an electrical insulator to form an isolation region in the first and second sections of the trench.
11. The method of claim 10 wherein the isolation region includes a void unfilled by the electrical insulator.
12. The method of claim 1 wherein forming the collector region in the substrate comprises:
selectively implanting ions into the substrate to dope the first semiconductor material in a portion of the substrate with a conductivity type.
13. The method of claim 1 wherein a shape of the section of the collector region is modified by the second etching process.