IP Library Granted Patent US 9,280,429
Granted Patent B2
US 9,280,429 · App. 14/135,467 · Granted Mar 8, 2016

Power fail latching based on monitoring multiple power supply voltages in a storage device

Inventors: Gregg S. Lucas (Tucson, AZ); Kenneth B. Delpapa (Natick, MA); Robert W. Ellis (Phoenix, AZ)
Assignee: SANDISK ENTERPRISE IP LLC
G06F11/2053G06F11/1402G06F11/2015G11C29/021G11C2029/0409
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Quick Facts
Patent No.
US 9,280,429
App. No.
14/135,467
Granted
Mar 8, 2016
Kind
B2
Abstract

The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Claims (63)

1. A method of protecting data in a storage device, the method comprising:

determining whether a first power supply voltage for the storage device provided to the storage device is out of range for a first time period;

determining whether a second power supply voltage for the storage device provided to the storage device is out of range for a second time period; and

in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition, and in accordance with the power fail condition, performing a power fail operation, the power fail operation including:

transferring data held in volatile memory in the storage device to non-volatile memory in the storage device; and

removing power from a plurality of controllers of the storage device.

2. The method of claim 1 , wherein the second power supply voltage is a voltage supplied for serial presence detect (SPD) functionality and the first power supply voltage is lower than the second power supply voltage.

3. The method of claim 1 , wherein determining whether the first power supply voltage provided to the storage device is out of range includes:

monitoring the first power supply voltage;

comparing the first power supply voltage with an under-voltage threshold, the under-voltage threshold determined in accordance with a target value of the first power supply voltage; and

in accordance with a determination that the first power supply voltage is less than the under-voltage threshold, determining the first power supply voltage is out of range.

4. The method of claim 3 , wherein determining the under-voltage threshold in accordance with the target value of the first power supply voltage includes:

determining a predefined percentage to use in determining the under-voltage threshold;

calculating a first value, the first value determined by multiplying the predefined percentage by the target value of the first power supply voltage;

calculating a second value, the second value determined by subtracting the first value from the target value of the first power supply voltage; and

setting the under-voltage threshold equal to the second value.

5. The method of claim 4 , wherein the predefined percentage varies in accordance with the target value of the first power supply voltage.

6. The method of claim 4 , wherein the predefined percentage is adjustable.

7. The method of claim 3 , wherein the under-voltage threshold differs from the target value of the first power supply voltage by different percentages of the target value of the first power supply voltage when the target value of the first power supply voltage is equal to distinct, predefined first and second voltages.

8. The method of claim 1 , wherein the first power supply voltage supports a higher level of performance by a supervisory controller of the storage device, when the supervisory controller is powered by the first power supply voltage, than a level of performance supported by the second power supply voltage when the supervisory controller is powered by the second power supply voltage.

9. The method of claim 1 , further comprising:

subsequent to completion of the power fail operation:

determining whether the first power supply voltage provided to the storage device is within range;

determining whether the second power supply voltage provided to the storage device is within range; and

in accordance with a determination that both the first power supply voltage and the second power supply voltage are within range, clearing the latched power fail condition.

10. The method of claim 1 , wherein the plurality of controllers on the storage device includes a memory controller and one or more flash controllers, the one or more flash controllers coupled by the memory controller to a host interface of the storage device.

11. The method of claim 10 , wherein transferring data held in volatile memory to non-volatile memory includes:

transferring data from the memory controller to the one or more flash controllers; and

transferring data from the one or more flash controllers to the non-volatile memory.

12. The method of claim 1 , wherein the power fail operation is performed to completion regardless of whether the first power supply voltage or the second power supply voltage returns to within range after the first and second time periods, respectively.

13. The method of claim 1 , wherein the storage device includes an energy storage device, and the power fail operation is performed using power from the energy storage device.

14. The method of claim 13 , wherein the energy storage device includes one or more capacitors.

15. The method of claim 1 , wherein the non-volatile memory comprises one or more flash memory devices.

16. The method of claim 1 , wherein the plurality of controllers on the storage device includes at least one non-volatile memory controller and at least one other memory controller other than the at least one non-volatile memory controller.

17. The method of claim 1 , wherein one of the plurality of controllers on the storage device maps double data rate (DDR) interface commands to serial advance technology attachment (SATA) interface commands.

18. The method of claim 1 , wherein the storage device includes a dual in-line memory module (DIMM) device.

19. The method of claim 1 , including:

determining whether the first power supply voltage is lower than a first under-voltage threshold for a first under-voltage time period; and

determining whether the first power supply voltage is higher than a first over-voltage threshold for a first over-voltage time period.

20. The method of claim 1 , including:

determining whether the second power supply voltage is lower than a second under-voltage threshold for a second under-voltage time period; and

determining whether the second power supply voltage is higher than a second over-voltage threshold for a second over-voltage time period.

21. A storage device, comprising:

an interface for operatively coupling the storage device with a host system;

the storage device configured to:

determine whether a first power supply voltage for the storage device provided to the storage device is out of range for a first time period;

determine whether a second power supply voltage for the storage device provided to the storage device is out of range for a second time period; and

in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latch a power fail condition, and in accordance with the power fail condition, perform a power fail operation, the power fail operation including:

transferring data held in volatile memory in the storage device to non-volatile memory in the storage device; and

removing power from a plurality of controllers of the storage device.

22. The storage device of claim 21 , wherein the second power supply voltage is a voltage supplied for serial presence detect (SPD) functionality and the first power supply voltage is lower than the second power supply voltage.

23. The storage device of claim 21 , wherein determining whether the first power supply voltage provided to the storage device is out of range includes:

monitoring the first power supply voltage;

comparing the first power supply voltage with an under-voltage threshold, the under-voltage threshold determined in accordance with a target value of the first power supply voltage; and

in accordance with a determination that the first power supply voltage is less than the under-voltage threshold, determining the first power supply voltage is out of range.

24. The storage device of claim 21 , further comprising a supervisory controller, wherein the first power supply voltage supports a higher level of performance by the supervisory controller, when the supervisory controller is powered by the first power supply voltage, than a level of performance supported by the second power supply voltage when the supervisory controller is powered by the second power supply voltage.

25. The storage device of claim 21 , wherein the storage device includes a dual in-line memory module (DIMM) device.

26. A non-transitory computer readable storage medium, storing one or more programs for execution by one or more processors of a storage device, the one or more programs including instructions for:

determining whether a first power supply voltage provided to the storage device is out of range for a first time period;

determining whether a second power supply voltage provided to the storage device is out of range for a second time period; and

in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition, and in accordance with the power fail condition, performing a power fail operation, the power fail operation including:

transferring data held in volatile memory in the storage device to non-volatile memory in the storage device; and

removing power from a plurality of controllers of the storage device.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069169/0572 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2024
From: SANDISK TECHNOLOGIES LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 066114/0298 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: SANDISK ENTERPRISE IP LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038295/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2014
From: LUCAS, GREGG S.; DELPAPA, KENNETH B.; ELLIS, ROBERT W.
To: SANDISK ENTERPRISE IP LLC
Reel/Frame 032041/0728 →
Continuity (2)
Provisional Application 61909952 · Nov 27, 2013
Related Publication 20150149825A1 · May 28, 2015