Integrated circuit structure with bulk silicon FinFET and methods of forming

1. A method of forming an integrated Circuit (IC) structure, the method comprising:

forming a layered dummy structure on a bulk substrate, wherein the layered dummy structure includes:

a first crystalline semiconductive layer;

a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the second crystalline semiconductive layer comprises a material distinct from the first crystalline semiconductive layer; and

a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the same material as the first crystalline semiconductive layer;

forming a semiconductor fin on the layered dummy structure, wherein the semiconductor fin comprises part of a finFET structure; and

selectively removing the layered dummy structure to form a cavity between the bulk substrate and the semiconductor fin.

2. The method of claim 1 , further comprising forming an insulator within the cavity, wherein a thickness of the formed insulator is substantially equal to a thickness of the layered dummy structure.

3. The method of claim 1 , wherein the forming of the layered dummy structure includes epitaxially growing the first and third crystalline semiconductive layers.

4. The method of claim 1 , further comprising forming an isolating film on the bulk substrate adjacent to the layered dummy structure.

5. The method of claim 4 , wherein the isolating film comprises silicon oxide (SiO 2 ).

6. Method of claim 1 , further comprising forming a transistor gate on the isolating film, and forming a spacer on the transistor gate and the semiconductor fin.

7. The method of claim 1 , further comprising removing a portion of the isolating film to expose the second crystalline semiconductive layer of the layered dummy structure.

8. The method of claim 1 , wherein the selective removing of the layered dummy structure includes chemically etching the second crystalline semiconductive layer of the layered dummy structure.

9. The method of claim 1 , wherein the selective removing of the layered dummy structure includes phosphorically etching one of the first and third crystalline semiconductive layers of the layered dummy structure.

10. The method of claim 1 , wherein the first and third crystalline semiconductive layers of the layered dummy structure comprise silicon germanium (SiGe), and the second crystalline semiconductive layer of the layered dummy structure comprises a crystalline semiconductor.

11. A method of forming an integrated circuit (IC) structure, the method comprising:

forming a first silicon germanium (SiGe) layer on a bulk substrate;

forming a semiconductor layer on the first SiGe layer;

forming a second SiGe layer on the semiconductor layer, wherein the first SiGe layer, the semiconductor layer, and the second SiGe layer comprise a layered dummy structure;

forming a finFET structure on the layered dummy structure, wherein the finFET structure includes a silicon fin and a transistor gate;

selectively removing the layered dummy structure to form a cavity between the bulk substrate and the finFET structure; and

forming an insulator within the cavity.

12. The method of claim 11 , further comprising:

forming an isolating film on the bulk substrate before selectively removing the layered dummy structure; and

forming a spacer on each of the silicon fin, the transistor gate, and the isolating film.

13. The method of claim 12 , further comprising removing a portion of the isolating film below the spacer to expose the semiconductor layer of the layered dummy structure.