Semiconductor device with non-isolated power transistor with integrated diode protection
A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.
1. A method of fabricating a non-isolated transistor, the method comprising:
forming a device separating region of the transistor in a semiconductor substrate, the substrate having a first conductivity type, the device separating region having a second conductivity type and defining an active area of the transistor, the second conductivity type being different from the first conductivity type; the device separating regions extending in a vertical orientation in the substrate but not across the active area in a lateral orientation to isolate the active area;
forming a body region of the transistor in the active area, the body region having the first conductivity type; and
forming source and drain regions of the transistor in the active area, the source region being situated on the body region, the source and drain regions having the second conductivity type;
wherein a spacing is defined between the device separating region and the body region to establish a first breakdown voltage lower than a second breakdown voltage in a conduction path between the source and drain regions.
2. The method of claim 1 , wherein forming the body region comprises:
implanting dopant of the first conductivity type in a first well region of the body region on which the source region is disposed; and
implanting the dopant of the first conductivity type in a second well region adjacent the first well region and spaced from the device separating region to establish the first breakdown voltage.
3. The method of claim 2 , wherein forming the body region comprises implanting the dopant of the first conductivity type in the first well at a different dopant concentration levels than the dopant of the first conductivity type in the second well of the body region.
4. The method of claim 1 , wherein forming the device separating region comprises forming a composite region comprising a separation well region and one or more contiguous deep well regions.
5. The method of claim 4 , wherein forming the device separating region comprises implanting a dopant of the second conductivity type in the separation well region and the one or more contiguous deep well regions, wherein the dopant in the separation well region is at a different dopant concentration level than the dopant in the one or more contiguous deep well regions.
6. The method of claim 4 , wherein forming the device separating region comprises forming the separation well region in the configuration of a ring surrounding the active area, wherein the separation well region is spaced from the body region to establish the first breakdown voltage.
7. The method of claim 4 , wherein at least one of the contiguous deep well regions spaced from the body region to establish the first breakdown voltage.
8. The method of claim 7 , wherein the at least one constituent deep well region extends laterally inward toward or under the body region.
9. The method of claim 4 , wherein forming the device separating region comprises forming an intermediate deep well region linking the separation well region and a second deep well region.
10. The method of claim 9 , wherein the intermediate deep well region or the second deep well region extends laterally inward toward or under the body region to define the spacing to establish the first breakdown voltage.
11. The method of claim 1 , further comprising configuring the conduction path such that the device is a laterally diffused metal-oxide-semiconductor (LDMOS) device.
12. The method of claim 1 , wherein the device separating region is electrically tied to the drain region such that the voltage at the drain region is clamped to the first breakdown voltage during a breakdown event.
13. A method of fabricating a non-isolated transistor, the method comprising:
forming a first semiconductor region in a semiconductor substrate having a first conductivity type to define an active area of the transistor, the first semiconductor region having a second conductivity type and extending in a vertical orientation in the substrate along a periphery of the active area but not extending across the active area in a lateral orientation to isolate the active area in the substrate, the first conductivity type being different from the second conductivity type;
forming a second semiconductor region having the second conductivity type in the active area;
forming a third semiconductor region having the first conductivity type in the active area; and
forming a fourth semiconductor region having the second conductivity type adjacent to the second semiconductor region;
wherein a spacing between the first and third semiconductor regions defines a diode depletion region having a first breakdown voltage lower than a second breakdown voltage.
14. The method of claim 13 , wherein
forming the third semiconductor region comprises forming a first well and a second well adjacent to the first well and spaced from the first semiconductor region to establish the first breakdown voltage; and
the method further comprises forming a fifth semiconductor region in the active area on the first well of the third semiconductor region, the fifth semiconductor region having the second conductivity type.
15. The method of claim 14 , wherein forming the third semiconductor region comprises doping the first well and the second sell with a dopant of the first conductivity type, wherein the dopant in the first well is at a different dopant concentration level than the dopant in the second well.
16. The method of claim 13 , wherein forming the first semiconductor region comprises forming a separation well in the configuration of a ring surrounding the active area and spaced from the third semiconductor region to establish the first breakdown voltage.
17. The method of claim 13 , wherein
forming the first semiconductor region comprises forming a composite comprising a separation well region in the substrate configured as a ring surrounding the active area, a deep well region, and an intermediate well region linking the separation well region and the deep well region; and
at least one of the intermediate well region and the deep well region extends laterally inward beyond the separation well region and toward or under the third semiconductor region to define a spacing between the first and the third semiconductor regions that defines the first breakdown voltage.
18. The method of claim 17 , wherein
forming the first semiconductor region comprises forming a well and a contact region on the well; and
the method further comprises forming a depletion region between the first semiconductor region and the third semiconductor region that reaches the contact region at the first breakdown voltage.