IP Library Granted Patent US 9,702,925
Granted Patent B2
US 9,702,925 · App. 14/514,449 · Granted Jul 11, 2017

Semiconductor device with upset event detection and method of making

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Quick Facts
Patent No.
US 9,702,925
App. No.
14/514,449
Granted
Jul 11, 2017
Kind
B2
Abstract

A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Claims (47)

1. A semiconductor device, comprising:

a substrate having a first conductivity type;

first electronic circuitry formed on a first major surface of the substrate;

a first doped region in the substrate, wherein the first doped region has a second conductivity type opposite the first conductivity type, and the first doped region underlies the first electronic circuitry and is separated from the first major surface of the substrate by a first portion of the substrate;

a first conductive contact formed between the first doped region and the first major surface of the substrate, the first conductive contact is in a first location of the first doped region;

a fault detection module coupled to the first doped region through the first conductive contact; and

a second doped region with the second conductivity type in the substrate, wherein the second doped region is between the first electronic circuitry and the first doped region, and the first doped region and the second doped region are separated from one another by a second portion of the substrate.

2. The semiconductor device of claim 1 , wherein the first doped region and the first portion of the substrate form a diode and a fault is detected when an electrical characteristic of the diode changes when a particle of sufficient energy impacts the substrate.

3. The semiconductor device semiconductor of claim 1 , wherein the second doped region covers a critical region of the first electronic circuitry.

4. The semiconductor device of claim 1 , wherein the first doped region spans a majority of area of the first major surface of the substrate.

5. The semiconductor device of claim 4 , further comprising:

a second conductive contact formed between the first doped region and the first major surface of the substrate, the second conductive contact is coupled to the fault detection module, and the second conductive contact is in a second location of the first doped region.

6. The semiconductor device of claim 1 , further comprising:

second electronic circuitry formed on the first major surface of the substrate;

a second doped region in the substrate, wherein the second doped region has a second conductivity type opposite the first conductivity type, and the second doped region underlies the second electronic circuitry and is separated from the first major surface of the substrate by a second portion of the substrate; and

a second conductive contact formed between the second doped region and the first major surface of the substrate, the second conductive contact is coupled to the fault detection module.

7. The semiconductor device of claim 1 , further comprising:

second electronic circuitry formed on the first major surface of the substrate;

a second doped region with the second conductivity type in the substrate, wherein the second doped region is under the second electronic circuitry and is separated from the first major surface of the substrate by a second portion of the substrate;

a second conductive contact formed between the second doped region and the first major surface of the substrate; and

a second fault detection module coupled to the second doped region through the second conductive contact.

8. A semiconductor device comprising:

a substrate;

first electronic circuitry formed on the substrate;

a first diode buried in the substrate under the first electronic circuitry; and

a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry; and

a second diode buried in the substrate under the first electronic circuitry and coupled to the first fault detection circuit.

9. The semiconductor device of claim 8 , further comprising:

a conductive contact formed between the first diode and a first major surface of the substrate, the conductive contact couples the first diode to the first fault detection circuit.

10. The semiconductor device of claim 8 , further comprising:

second electronic circuitry formed on the substrate; and

a second diode buried in the substrate under the second electronic circuitry and coupled to the first fault detection circuit.

11. The semiconductor device of claim 8 , further comprising:

second electronic circuitry formed on the substrate;

a second fault detection circuit;

a second diode buried in the substrate under the second electronic circuitry and coupled to the second fault detection circuit.

12. The semiconductor device of claim 8 , wherein the substrate has a first conductivity type and the first diode includes a portion of the substrate and a doped region with a second conductivity type that is opposite the first conductivity type.

13. The semiconductor device of claim 12 , wherein the portion of the substrate is between the doped region and the first electronic circuitry.

14. The device of claim 8 , wherein the first fault detection circuit detects a change in an electrical characteristic of the first diode in response to the energetic particle strikes.

15. The device of claim 8 , wherein an area of the first diode extends over a majority of area of the substrate.

16. A method comprising:

forming a first diode in a semiconductor substrate, wherein the first diode is buried in the semiconductor substrate;

coupling a first fault detection circuit to the first diode, wherein an electrical characteristic of the first diode has a change when a particle impacts the semiconductor substrate with a measurable level of energy, and the first fault detection circuit detects the change in the electrical characteristic;

forming a second diode in the semiconductor substrate, wherein the second diode is buried in the semiconductor substrate in a location that is different than a location of the first diode; and

coupling the second diode to one of a group consisting of: the first fault detection circuit and a second fault detection circuit.

17. The method of claim 16 , further comprising:

forming electronic circuitry on the semiconductor substrate above the first diode.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: HALL, MARK D.; ANDERSON, STEVEN G.H.; SHROFF, MEHUL D.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034770/0847 →