IP Library Granted Patent US 9,550,664
Granted Patent B2
US 9,550,664 · App. 14/574,784 · Granted Jan 24, 2017

Reducing MEMS stiction by increasing surface roughness

Inventors: Ruben B. Montez (Cedar Park, TX); Robert F. Steimle (Austin, TX)
Assignee: NXP USA, INC.
B81B3/001B81B2201/0235B81B2203/0181B81C2201/115
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Quick Facts
Patent No.
US 9,550,664
App. No.
14/574,784
Granted
Jan 24, 2017
Kind
B2
Abstract

A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces, such as a travel stop and travel stop region, that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of the travel stop region. This is achieved by depositing a polysilicon layer over a dielectric layer using gaseous hydrochloric acid as one of the reactants. A subsequent etch back is performed to further increase the roughness. The deposition of polysilicon and subsequent etch back may be repeated one or more times in order to obtain the desired roughness. A final polysilicon layer may then be deposited to achieve a desired thickness. This final polysilicon layer is patterned to form the travel stop regions. The rougher surface decreases the surface area available for contact and, in turn, decreases the area through which stiction can be imparted.

Claims (42)

1. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming an insulating layer over a substrate;

depositing a first polysilicon layer on the insulating layer by reacting a silicon-containing gas, gaseous hydrochloric acid, and hydrogen for a first duration of time at a first temperature, wherein, during the deposition, the gaseous hydrochloric acid is at least 15% of a total flow of the gaseous hydrochloric acid and the silicon-containing gas;

etching the first polysilicon layer using gaseous hydrochloric acid and hydrogen for a second duration of time at a second temperature;

depositing a second polysilicon layer over the etched first polysilicon layer by reacting the silicon-containing gas and hydrogen for a third duration of time at a third temperature; and

patterning the second polysilicon layer and the first polysilicon layer to form a travel stop region of the MEMS device.

2. The method of claim 1 , further comprising:

forming a sacrificial layer over the travel stop region; and

forming a third polysilicon layer on the sacrificial layer.

3. The method of claim 2 , further comprising removing the sacrificial layer to separate the third polysilicon layer from the travel stop region.

4. The method of claim 1 , wherein after the etching the first polysilicon layer and prior to depositing the second polysilicon layer, the method further comprises:

depositing a third polysilicon layer on the etched first polysilicon layer by reacting the silicon-containing gas, gaseous hydrochloric acid, and hydrogen for a fourth duration of time at a fourth temperature, wherein, during the deposition of the third polysilicon layer, the gaseous hydrochloric acid is at least 15 % of a total flow of the gaseous hydrochloric acid and the silicon-containing gas; and

etching the third polysilicon layer using gaseous hydrochloric acid and hydrogen for a fifth duration of time at a fifth temperature, wherein the second polysilicon layer is deposited over the etched third polysilicon layer.

5. The method of claim 4 , wherein the first duration of time and fourth duration of time is each in a range of 5 to 15 minutes and wherein the first temperature and the fifth temperature is each at least 630 degrees Celsius.

6. The method of claim 4 , wherein the depositing the third polysilicon layer is performed by also reacting a dopant gas.

7. The method of claim 1 , wherein the first duration of time is in a range of 5 to 15 minutes and wherein the first temperature is at least 630 degrees Celsius.

8. The method of claim 7 , wherein the depositing the first polysilicon layer is performed by also reacting a dopant gas.

9. The method of claim 7 , wherein the second duration of time is in a range of 10 to 40 seconds and the second temperature is at least 950 degrees Celsius.

10. The method of claim 1 , wherein the deposited first polysilicon layer has a mean thickness of 40 nm with a tallest peak of at least 55nm and a lowest valley of at most 35 nm.

11. The method of claim 10 , wherein the travel stop region has a mean thickness of 350 nm with a tallest peak of at least 420 nm and a lowest valley of at most 300 nm.

12. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming an insulating layer over a substrate;

depositing a first semiconductor layer on the insulating layer by reacting a semiconductor-containing gas, gaseous hydrochloric acid, and hydrogen for a first duration of time at a first temperature, wherein, during the deposition, the gaseous hydrochloric acid is at least 15% of a total flow of the gaseous hydrochloric acid and the semiconductor-containing gas;

etching the first semiconductor layer using gaseous hydrochloric acid and hydrogen for a second duration of time at a second temperature;

depositing a second semiconductor layer over the etched first polysilicon layer by reacting the semiconductor-containing gas and hydrogen for a third duration of time at a third temperature; and

patterning the second semiconductor layer and the first semiconductor layer to form a travel stop region of the MEMS device.

13. The method of claim 12 , wherein after the etching the first semiconductor layer and prior to depositing the second semiconductor layer, the method further comprises:

depositing a third semiconductor layer on the etched first semiconductor layer by reacting the semiconductor-containing gas, gaseous hydrochloric acid, and hydrogen for a fourth duration of time at a fourth temperature, wherein, during the deposition of the third polysilicon layer, the gaseous hydrochloric acid is at least 15% of a total flow of the gaseous hydrochloric acid and the semiconductor-containing gas; and

etching the third semiconductor layer using gaseous hydrochloric acid and hydrogen for a fifth duration of time at a fifth temperature, wherein the second semiconductor layer is deposited over the etched third semiconductor layer.

14. The method of claim 12 , wherein the depositing the third semiconductor layer is performed by also reacting a dopant gas.

15. The method of claim 12 , wherein the semiconductor-containing gas comprises one of silicon or germanium.

16. A method of manufacturing a microelectromechanical systems (MEMS) device comprising:

forming a fixed surface comprising

a first semiconductor layer over a substrate, wherein the first semiconductor layer has a mean thickness of 350 nm with a tallest peak of at least 420 nm and a lowest valley of at most 300 nm; and

a first insulating layer over at least a portion of the first semiconductor layer; and

forming a movable body comprising a second semiconductor layer providing a major surface facing the first semiconductor layer.

17. The method of claim 16 wherein forming the movable body comprises:

forming a pivoting proof mass of a teeter-totter accelerometer;

forming a travel stop feature, configured to contact the first semiconductor layer to prevent over rotation of the pivoting proof mass, and comprising a portion of the major surface facing the first semiconductor layer.

18. The method of claim 16 wherein the first semiconductor layer comprises one of silicon or germanium.

19. The method of claim 18 wherein the second semiconductor layer comprises one of silicon or germanium.

20. The method of claim 16 wherein the MEMS device comprises at least a portion of an accelerometer.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: MONTEZ, RUBEN B.; STEIMLE, ROBERT F.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034545/0832 →
Continuity (1)
Related Publication 20160176707A1 · Jun 23, 2016